System for reducing peak power during scan shift at the local level for scan based tests

• US 9,395,414 B2
• Filed: 12/28/2012
• Issued: 07/19/2016
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sonawane, Milind, Puvvada, Satya, Sanghani, Amit
• Primary Examiner(s): Ton, David
• Application Number:
  US13/730,551
• Publication Number:
  US 20140189452A1
• Time in Patent Office: 1,299 Days
• Field of Search: 365/233.1, 715/741, 714/726, 714/727, 714/729, 714/731
• US Class Current: 1/1
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, where each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, where each partition receives a respective one of the plurality of second clock signals and where the plurality of second clock signals are staggered where each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.

Claims

1. A method for performing scan-based tests, the method comprising:

routing data serially to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, wherein each partition of the plurality of partitions comprises a plurality of internal scan chains;

deserializing the data;

generating a plurality of second clock signals operating at a second frequency using the first clock signal, wherein each partition receives a respective one of the plurality of second clock signals at each partition, and wherein the plurality of second clock signals are time-staggered; and

shifting in the data into the internal scan chains of the plurality of partitions at the rate of the second frequency using the plurality of second clock signals.

2. The method of claim 1, wherein the routing is performed from a plurality of I/O ports to the plurality of partitions.

3. The method of claim 2 further comprising:

serializing output data to route the output data from the plurality of partitions to the plurality of I/O ports; and

shifting out the output data from the internal scan chains of the plurality of partitions serially at the rate of the first frequency, wherein each of the plurality of partitions uses the first clock signal to perform the shifting out.

4. The method of claim 1 wherein the first frequency is a multiple of the second frequency.

5. The method of claim 1, wherein the generating comprises:

enabling the plurality of second clock signals using clock stagger enable signals, wherein each clock stagger enable signal is used to control a clock gating cell for each partition.

6. The method of claim 5 wherein each clock stagger enable signal controls the clock gating cell for a partition wherein only one pulse of a second clock signal is generated every N cycles of the first clock signal, where N is the quotient of the first frequency and the second frequency.

7. The method of claim 1 further comprising decompressing deserialized data before the shifting in the data into the internal scan chains of the plurality of partitions.

8. A method for performing scan-based tests, the method comprising:

routing data serially to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, wherein the plurality of partitions comprises a plurality of internal scan chains;

deserializing the data;

generating a plurality of second clock signals operating at a second frequency using the first clock signal, wherein each partition receives a respective one of the plurality of second clock signals at each partition, and wherein the plurality of second clock signals are time-staggered; and

shifting in the data into the internal scan chains of the plurality of partitions at the rate of the second frequency using the plurality of second clock signals.

9. The method of claim 8, wherein the routing is performed from a plurality of I/O ports to the plurality of partitions.

10. The method of claim 9 further comprising:

serializing output data to route the output data from the plurality of internal scan chains to the plurality of I/O ports; and

shifting out the output data from the internal scan chains of the plurality of partitions serially at the rate of the first frequency, wherein each of the plurality of partitions uses the first clock signal to perform the shifting.

11. The method of claim 8 wherein the first frequency is a multiple of the second frequency.

12. The method of claim 8 wherein the generating comprises:

enabling the plurality of second clock signals using clock stagger enable signals, wherein each clock stagger enable signal is used to control a clock gating cell for each partition.

13. The method of claim 12 wherein each clock stagger enable signal controls the clock gating cell for an internal scan chain wherein only one pulse of a second clock signal is generated every N cycles of the first clock signal, where N is the quotient of the first frequency and the second frequency.

14. The method of claim 8 further comprising decompressing deserialized data before the shifting in the data into the internal scan chains of the plurality of partitions.

15. A system for performing scan-based tests, the system comprising:

a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of I/O ports;

a integrated circuit under test comprising a plurality of partitions, wherein each partition comprises a plurality of internal scan chains, and wherein the tester processor is operable to route data serially to the plurality of partitions using a first clock signal operating at a first frequency;

a plurality of gating cells operable to use the first clock signal to generate a plurality of second clock signals operating at a second frequency, wherein each partition receives a respective second clock signal and wherein the plurality of second clock signals are time-staggered; and

a deserializer module operable to deserialize the data for loading into internal scan chains within each partition, wherein the deserializer module is further operable to shift in the data into the internal scan chains of the plurality of partitions at the rate of the second frequency using the plurality of second clock signals.

16. The system as described in claim 15, wherein the plurality of partitions are communicatively coupled to the plurality of I/O ports, and further wherein the tester processor is operable to route data serially from the plurality of I/O ports to the plurality of partitions, and wherein each of the plurality of partitions uses a respective second clock signal it receives to shift in the data.

17. The system as described in claim 15 further comprising a serializer module operable to serialize output n data to route the output data to the plurality of I/O ports from the plurality of partitions and wherein the serializer module is further operable to shift out the output data from the plurality of internal scan chains of the plurality of partitions serially at the rate of the first frequency, wherein each of the plurality of partitions uses the first clock signal to perform the shift out.

18. The system as described in claim 15 wherein the first frequency is a multiple of the second frequency.

19. The system as described in claim 18, wherein the first frequency is 4 times a magnitude of the second frequency.

20. The system as described in claim 15 further comprising a stagger control module, wherein the stagger control module enables the plurality of second clock signals using clock stagger enable signals, and wherein each clock stagger enable signal is used to control a clock gating cell for each partition.

21. The system as described in claim 20 wherein each clock stagger enable signal controls the clock gating cell for a partition wherein only one pulse of a second clock signal is generated every N cycles of the first clock signal, where N is the quotient of the first frequency and the second frequency.

22. The system as described in claim 15 wherein the system further comprises a decompressor module operable to decompress deserialized data before the shift in of the data into the internal scan chains of the plurality of partitions.