Signal comparison apparatus and method of controlling same

• US 9,395,746 B2
• Filed: 06/03/2015
• Issued: 07/19/2016
• Est. Priority Date: 12/08/2014
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chung, Yung-Hui, Chen, Bo-Wei
• Primary Examiner(s): Puentes, Daniel
• Application Number:
  US14/729,063
• Publication Number:
  US 20160161978A1
• Time in Patent Office: 412 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew

Abstract

A signal comparison apparatus and a method of controlling the same are provided. The signal comparison apparatus includes a first comparator, a self-timed clock generator and a controller. The first comparator is controlled by a start signal to compare differences of first input signals and generate output signals. The self-timed clock generator receives the output signals to generate a self-timed clock signal. The controller receives the self-timed clock signal and calculates a time interval of the self-timed clock signal which responds to the first input signals of the first comparator, and determines whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal. When the time interval is equal to or larger than the threshold time, the controller outputs the metastable detection signal as the start signal, such that the first comparator continue comparing the next differences of the first input signals.

Claims

1. A signal comparison apparatus, comprising:

a first comparator, configured to receive at least two first input signals and be controlled by a start signal to compare differences of the at least two first input signals to generate an output signal based on the start signal;

a self-timed clock generator, coupled to the first comparator and configured to receive the output signals and generate a self-timed clock signal according to the output signals; and

a controller, coupled to the self-timed clock generator and configured to receive the self-timed clock signal, calculate a time interval of the self-timed clock signal and determine whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal, wherein the time interval responds to the at least two first input signals, and the controller outputs the metastable detection signal as the start signal when the time interval is equal to or larger than the threshold time, so as to enable the first comparator to continue comparing the next differences of the at least two first input signals.

2. The signal comparison apparatus as recited in claim 1, wherein the controller further receives at least two second input signals, and the controller comprises:

a metastable detector, configured to receive the start signal or the at least two second input signals to generate the metastable detection signal, wherein the start signal responds to the self-timed clock signal, and the metastable detector calculates the time interval in which the self-timed clock signal is located at a voltage level and determines whether the time interval is equal to or larger than the threshold time to generate the metastable detector; and

a selector, configured to receive the self-timed clock signal and coupled to the metastable detector to receive the metastable detection signal, wherein the selector selects the metastable detection signal as the start signal when the time interval of the self-timed clock signal is equal to or larger than the threshold time, or the selector selects the self-timed clock signal as the start signal;

wherein the threshold time responds to the start signal or the at least two second input signals.

3. The signal comparison apparatus as recited in claim 2, wherein the metastable detector comprises:

a second comparator, configured to receive the start signal and the start signal with an opposite phase and be controlled by the start signal, wherein the start signal and the start signal with the opposite phase are compared based on the start signal to generate a differential output signal; and

a logic gate, coupled to the second comparator and configured to receive the differential output signal and perform logic operation on the differential output signal to generate the metastable detection signal.

4. The signal comparison apparatus as recited in claim 3, wherein the logic gate comprises a NAND-gate or an OR-gate.

5. The signal comparison apparatus as recited in claim 3, wherein a circuit structure of the second comparator is substantially equivalent to the circuit structure of the first comparator.

6. The signal comparison apparatus as recited in claim 5, wherein a processing speed of the second comparator is lower than the processing speed of the first comparator.

7. The signal comparison apparatus as recited in claim 2, wherein the metastable detector comprises:

a second comparator, configured to receive at least two second input signals and be controlled by the start signal to compare differences of the at least two second input signals, so as to generate a differential output signal; and

a logic gate, coupled to the second comparator configured to receive the differential output signal and perform logic operation on the differential output signal to generate the metastable detection signal.

8. The signal comparison apparatus as recited in claim 7, wherein the logic gate comprises a NAND-gate or an OR-gate.

9. The signal comparison apparatus as recited in claim 7, wherein a circuit structure of the second comparator is substantially equivalent to the circuit structure of the first comparator.

10. The signal comparison apparatus as recited in claim 9, wherein a processing speed of the second comparator is lower than the processing speed of the first comparator.

11. The signal comparison apparatus as recited in claim 2, wherein the selector comprises:

a NOR-gate, configured to receive the self-timed clock signal with an opposite-phase and the metastable detection signal to generate the start signal.

12. The signal comparison apparatus as recited in claim 2, wherein the selector comprises:

an AND-gate, configured to receive the self-timed clock signal and the metastable detection signal with an opposite-phase to generate the start signal.

13. The signal comparison apparatus as recited in claim 1, wherein the output signal is a differential output signal.

14. The signal comparison apparatus as recited in claim 13, wherein the self-timed clock generator further receives an enable signal, and the self-timed clock generator comprises:

an OR-gate, configured to receive the differential output signal to generate a valid comparison signal; and

a NOR-gate, configured to receive the enable signal, and coupled to the OR-gate to receive the valid comparison signal and generate the self-timed clock signal.

15. The signal comparison apparatus as recited in claim 13, wherein the self-timed clock generator further receives an enable signal, and the self-timed clock generator comprises:

a NAND-gate, configured to receive the differential output signal to generate a valid comparison signal; and

a NOR-gate, configured to receive the enable signal, and coupled to the NAND-gate to receive the valid comparison signal and generate the self-timed clock signal.

16. A method of controlling a signal comparison apparatus, comprising:

receiving at least two first input signals;

comparing differences of the at least two first input signals to generate an output signal based on a start signal;

generating a self-timed clock signal according to the output signal;

calculating a time interval of the self-timed clock signal, wherein the time interval responds to the at least two first input signals; and

determining whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal;

wherein the metastable detection signal is selected as the start signal when the time interval is equal to or larger than the threshold time, so as to enable the signal comparison apparatus to continue comparing the next differences of the at least two first input signals.

17. The method of controlling the signal comparison apparatus as recited in claim 16, wherein the method for generating the start signal further comprises:

selecting the self-timed clock signal as the start signal when the time interval is smaller than the threshold time.

18. The method of controlling the signal comparison apparatus as recited in claim 17, further comprising:

receiving at least two second input signals;

wherein the threshold time responds to the start signal or the at least two second input signals.

19. The method of controlling the signal comparison apparatus as recited in claim 18, wherein the threshold time responds to a difference between the at least two second input signals,

the threshold time being shorter when the difference between the at least two second input signals is larger;

and

the threshold time being longer when the difference between the at least two second input signals is smaller.

20. The method of controlling the signal comparison apparatus as recited in claim 16, wherein the method for generating the start signal comprises:

performing a logical NOR operation on the self-timed clock signal with an opposite phase and the metastable detection signal to generate the start signal.

21. The method of controlling the signal comparison apparatus as recited in claim 16, wherein the method for generating the start signal comprises:

performing a logical AND operation on the self-timed clock signal and the opposite-phase metastable detection signal to generate the start signal.

22. The method of controlling the signal comparison apparatus as recited in claim 16, wherein the output signal is a differential output signal.

23. The method of controlling the signal comparison apparatus as recited in claim 22, further comprising:

receiving an enable signal,

wherein the method of generating the self-timed clock signal comprises;

performing a logical OR operation on the differential output signal to generate a valid comparison signal; and

performing a logical NOR operation on the enable signal and the valid comparison signal to generate the self-timed clock signal.

24. The method of controlling the signal comparison apparatus as recited in claim 22, further comprising:

receiving an enable signal,

wherein the method of generating the self-timed clock signal comprises;

performing a logical NAND operation on the differential output signal to generate a valid comparison signal; and

performing a logical NOR operation on the Enable signal and the valid comparison signal to generate the self-timed clock signal.