Total platform power control

• US 9,395,774 B2
• Filed: 12/28/2012
• Issued: 07/19/2016
• Est. Priority Date: 12/28/2012
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rotem, Efraim, Hermerding, James G. II, Ma, Ruoying, Rodriguez, Jorge P., Rosenzweig, Nir
• Primary Examiner(s): Elamin, M
• Application Number:
  US13/730,291
• Publication Number:
  US 20140189376A1
• Time in Patent Office: 1,299 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

logic, at least a portion of which is in hardware, to cause modification to power consumption by one or more processor cores of a processor and one or more components coupled to the processor based on a total platform power consumption value,

wherein a platform is to comprise the processor and the one or more components, wherein the total platform power consumption value is to be determined based on a signal from a first Analog to Digital Converter (ADC) and a second ADC, wherein the first ADC or second ADC is to generate the signal based on a power measurement by the first ADC or the second ADC, wherein the first ADC is to be coupled to a smart brick and the second ADC is to be coupled to a battery.

2. The apparatus of claim 1, wherein the one or more components are to comprise one or more of:

chipset, platform control hub, memory controller, graphics logic, and memory.

3. The apparatus of claim 1, wherein the logic is to comprise one or more of:

a power management unit, a power control unit, an embedded controller, and a node manager.

4. The apparatus of claim 1, wherein the total platform power consumption value is determined based on one or more of:

a first value, corresponding to a power supply power consumption;

a second value, corresponding to combined battery and power supply power consumption; and

a third value corresponding to a battery power consumption.

5. The apparatus of claim 1, wherein the total platform power consumption value is determined based on one or more power consumption values that are set by one or more of:

a basic input/output system, communication from a smart brick, and a battery.

6. The apparatus of claim 5, wherein the smart brick is to comprise a power supply that is capable to communicate its maximum output.

7. The apparatus of claim 5, wherein the battery is to comprise a smart battery that is capable to report its charge level.

8. The apparatus of claim 1, wherein the total platform power consumption value is determined based on a plurality of power consumption values corresponding to the processor and the one or more components of the platform.

9. The apparatus of claim 1, further comprising one or more sensors to detect variations in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

10. The apparatus of claim 1, wherein one or more of:

the logic, the one or more processor cores of the processor, and a memory are on a single integrated circuit.

31. The apparatus of claim 1, wherein the total platform power consumption value is determined further based on a power consumption value that is set by a node manager.

32. The apparatus of claim 1, wherein at least one of the first ADC or the second ADC is to sense a voltage across a resistor to perform the power measurement, wherein the resistor is to be coupled between a power supply and the battery or the smart brick.

11. A method comprising:

causing modification to power consumption by one or more processor cores of a processor and one or more components coupled to the processor based on a total platform power consumption value,

wherein a platform comprises the processor and the one or more components, wherein the total platform power consumption value is determined based on a signal from a first Analog to Digital Converter (ADC) and a second ADC, wherein the first ADC or second ADC generates the signal based on a power measurement by the first ADC or the second ADC, wherein the first ADC is coupled to a smart brick and the second ADC is coupled to a battery.

12. The method of claim 11, further comprising determining the total platform power consumption value based on one or more of:

a first value, corresponding to a power supply consumption;

a second value, corresponding to combined battery and power supply power consumption; and

a third value corresponding to a battery power consumption.

13. The method of claim 11, further comprising determining the total platform power consumption value based on one or more power consumption values that are set by one or more of:

a basic input/output system, communication from a smart brick, and a battery.

14. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

cause modification to power consumption by one or more processor cores of a processor and one or more components coupled to the processor based on a total platform power consumption value,

wherein a platform comprises the processor and the one or more components, wherein the total platform power consumption value is determined based on a signal from a first Analog to Digital Converter (ADC) and a second ADC, wherein the first ADC or second ADC generates the signal based on a power measurement by the first ADC or the second ADC, wherein the first ADC is coupled to a smart brick and the second ADC is coupled to a battery.

15. The non-transitory computer-readable medium of claim 14, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to determine the total platform power consumption value based on one or more of:

a first value, corresponding to a power supply consumption;

a second value, corresponding to combined battery and power supply power consumption; and

a third value corresponding to a battery power consumption.

16. The non-transitory computer-readable medium of claim 14, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to determine the total platform power consumption value based on one or more power consumption values that are set by one or more of:

a basic input/output system, communication from a smart brick, and a battery.

17. The non-transitory computer-readable medium of claim 14, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to determine the total platform power consumption value based on a plurality of power consumption values corresponding to the processor and the one or more components of the platform.

18. The non-transitory computer-readable medium of claim 14, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause one or more sensors to detect variations in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

19. A system comprising:

a processor having a plurality of processor cores;

memory to store information corresponding power consumption of one or more components of the system;

logic, at least a portion of which is in hardware, to cause modification to power consumption by at least one of the plurality of processor cores of the processor and one or more components coupled to the processor based on a total platform power consumption value that is determined at least in part based on the stored information,

wherein a platform is to comprise the processor and the one or more components, wherein the total platform power consumption value is to be determined based on a signal from a first Analog to Digital Converter (ADC) and a second ADC, wherein the first ADC or second ADC is to generate the signal based on a power measurement by the first ADC or the second ADC, wherein the first ADC is to be coupled to a smart brick and the second ADC is to be coupled to a battery.

20. The system of claim 19, wherein the one or more components are to comprise one or more of:

chipset, platform control hub, memory controller, graphics logic, and the memory.

21. The system of claim 19, wherein the logic is to comprise one or more of:

a power management unit, a power control unit, an embedded controller, and a node manager.

22. The system of claim 19, wherein the total platform power consumption value is determined based on a first value corresponding to a power supply power consumption.

23. The system of claim 22, wherein the total platform power consumption value is determined based on a second value corresponding to combined battery and power supply capabilities.

24. The system of claim 19, wherein the total platform power consumption value is determined based on one or more power consumption values that are set by one or more of:

a basic input/output system, communication from a smart brick, and a battery.

25. The system of claim 24, wherein the smart brick is to comprise a power supply that is capable to communicate its maximum output.

26. The system of claim 24, wherein the battery is to comprise a smart battery that is capable to report its charge level.

27. The system of claim 19, wherein the total platform power consumption value is determined based on a plurality of power consumption values corresponding to the processor and the one or more components of the platform.

28. The system of claim 19, further comprising one or more sensors to detect variations in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

29. The system of claim 19, further comprising an audio device coupled to the memory.

30. The system of claim 19, wherein one or more of:

the logic, the one or more processor cores of the processor, and a memory are on a single integrated circuit.