Large multiplier for programmable logic device

• US 9,395,953 B2
• Filed: 06/10/2014
• Issued: 07/19/2016
• Est. Priority Date: 12/05/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin, Tharmalingam, Kumara
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US14/300,436
• Publication Number:
  US 20140289293A1
• Time in Patent Office: 770 Days
• Field of Search: 708/620, 708/625
• US Class Current: 1/1
• CPC Class Codes: G06F 7/52 Multiplying; Dividing G06F7/483 - G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Abstract

A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.

Claims

1. For use in an integrated circuit having a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of multipliers, a method of performing a multiplication operation of a second size larger than said first size, said method comprising:

decomposing said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size;

performing a multiplication operation of a first one of said different sizes using multipliers in a first one of said units;

performing a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes using a multiplier in a second one of said units;

performing a plurality of multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes, using, for each respective one of said multiplication operations of said third one of said different sizes, a respective subset of said multipliers in a third one of said units; and

adding results of said multiplication operations of said first, second and third ones of said different sizes.

2. The method of claim 1 wherein:

said integrated circuit is a programmable logic device; and

said adding comprises adding said results in general-purpose programmable logic of said programmable logic device.

3. The method of claim 1 wherein said adding comprises aligning outputs of said plurality of multiplication operations of said third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes.

4. The method of claim 3 wherein:

said performing a plurality of multiplication operations of said third one of said different sizes comprises, for each respective one of said multiplication operations of said third one of said different sizes;

forming a respective most significant bit partial product, and

forming a respective least significant bit partial product;

said aligning comprises shifting each respective most significant bit partial product without shifting any respective least significant bit partial product; and

said addition within said third one of said units excludes further shifting of partial products.

5. The method of claim 4 further comprising selecting control signals to perform said shifting and said addition without further shifting.

6. The method of claim 1 wherein each said specialized processing block comprises two of said units.

7. The method of claim 6 wherein said adding comprises performing said adding substantially in one of said specialized processing blocks.

8. The method of claim 7 wherein said adding comprises compressing.

9. An integrated circuit having a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of multipliers, wherein:

said integrated circuit is configured to perform a multiplication operation of a second size larger than said first size by decomposition of said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size; and

said integrated circuit comprises;

multipliers in a first one of said units configured to perform a multiplication operation of a first one of said different sizes,

a multiplier in a second of one said units configured to perform a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes;

a plurality of respective subsets of said multipliers in a third one of said units configured to perform a plurality of respective multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes; and

circuitry configured to add results of said multiplication operations of said first, second and third ones of said different sizes.

10. The integrated circuit of claim 9 wherein:

said integrated circuit is a programmable logic device; and

said circuitry configured to add is configured in general-purpose programmable logic of said programmable logic device.

11. The integrated circuit of claim 9 wherein said circuitry configured to add comprises a shifter configured to align outputs of said plurality of multiplication operations of a third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes.

12. The integrated circuit of claim 11 wherein:

each of said respective subsets of said multipliers in said third one of said units configured to perform one of said respective multiplication operations of said third one of said different sizes forms a respective most significant bit partial product, and forms a respective least significant bit partial product;

said shifter shifts each respective most significant bit partial product without shifting any least significant bit partial product; and

said circuitry configured to add excludes further shifting of partial products.

13. The integrated circuit of claim 12 further comprising selectors responsive to selection control signals to control said shifter and said circuitry configured to add.

14. The integrated circuit of claim 9 wherein each of said specialized processing blocks comprises two of said units.

15. The integrated circuit of claim 14 wherein said circuitry configured to add is located substantially within one said specialized processing block.

16. The integrated circuit of claim 9 wherein circuitry configured to add comprises a compressor.

17. A non-transitory data storage medium encoded with non-transitory machine-executable instructions for performing a method of programmably configuring an integrated circuit to perform a multiplication operation of a second size larger than said first size by decomposition of said multiplication operation of said second size into a plurality of multiplication operations of different sizes, each of said different sizes being smaller than said second size, wherein said integrated circuit has a plurality of specialized processing blocks, each of said specialized processing blocks having a plurality of multipliers of a first size arranged in units of multipliers, said instructions comprising:

instructions for configuring multipliers in a first one of said units to perform a multiplication operation of a first one of said different sizes;

instructions for configuring a multiplier in a second of one said units to perform a multiplication operation of a second one of said different sizes smaller than said first one of said different sizes;

instructions for configuring a plurality of respective subsets of said multipliers in a third one of said units configured to perform a plurality of respective multiplication operations of a third one of said different sizes, smaller than said first one of said different sizes and larger than said second one of said different sizes; and

instructions for configuring circuitry to add results of said multiplication operations of said first, second and third ones of said different sizes.

18. The data storage medium of claim 17 wherein:

said instructions for configuring an integrated circuit are for configuring a programmable logic device; and

said instructions for configuring circuitry to add comprise instructions for configuring general-purpose programmable logic of said programmable logic device to add said results.

19. The data storage medium of claim 17 wherein said instructions for configuring circuitry to add comprise instructions for configuring a shifter to align outputs of said plurality of multiplication operations of a third one of said different sizes for addition within said third one of said units, to form a result of said multiplication operations of said third one of said different sizes.

20. The data storage medium of claim 19 comprising:

instructions to configure each of said respective subsets of said multipliers in said third one of said units to perform one of said respective multiplication operations of said third one of said different sizes forms a respective most significant bit partial product, and forms a respective least significant bit partial product;

instructions to configure said shifter to shift each respective most significant bit partial product without shifting any least significant bit partial product; and

instructions to configure said circuitry configured to add to exclude further shifting of partial products.

21. The data storage medium of claim 20 wherein said instructions further comprise instructions to configure selectors responsive to selection control signals to control said shifter and said circuitry configured to add.

22. The data storage medium of claim 17 wherein:

said instructions are for configuring a programmable logic device wherein each of said specialized processing blocks comprises two of said units; and

said instructions configure said circuitry to add substantially within one of said specialized processing blocks.

23. The data storage medium of claim 17 wherein said instructions to configure circuitry configured to add comprise instructions to configure a compressor.