Group based codes for multi-dimensional recording (MDR)

• US 9,396,062 B1
• Filed: 04/04/2014
• Issued: 07/19/2016
• Est. Priority Date: 04/04/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Sridhara, Deepak, Radich, William, Patapoutian, Ara, Feldman, Timothy R, Gaertner, Mark
• Primary Examiner(s): Abraham, Esaw
• Application Number:
  US14/245,886
• Time in Patent Office: 837 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.

Claims

1. An apparatus comprising:

a circuit configured to;

receive data from at least two inputs which are configured to access two or more memory groups at one time;

determine inner codes and outer codes corresponding to the data; and

perform error correction operations on the data based on the inner codes and the outer codes.

2. The apparatus of claim 1 further comprising:

the circuit configured to;

receive first data at a first input of the at least two inputs, the first data including first segments of data, each first segment having multiple symbols;

receive second data at a second input of the at least two inputs, the second data including other segments of data, each other segment having multiple symbols;

the inner codes include inner codewords, each inner codeword contains parity data corresponding to a pre-determined first segment and a pre-determined other segment, the parity data includes data for correcting X number of errors in the pre-determined first segment or the pre-determined other segment; and

the outer codes contain M number of symbols from pre-determined segments of the first data and the second data, the outer codes include data for correcting N number of errors of symbols.

3. The apparatus of claim 2 comprising the circuit further configured to:

encode the first data and the second data to produce the outer codes.

4. The apparatus of claim 2 comprising the circuit further configured to:

receive the first data and the second data from a multi-dimensional reading (MDR) system having at least a first read element corresponding to the first input and a second read element corresponding to the second input; and

the inner codewords include parity data calculated based on multiple segments.

5. The apparatus of claim 2 comprising the circuit further configured to:

receive the first data and the second data from a multi-dimensional reading (MDR) system having at least a first read element corresponding to the first input and a second read element corresponding to the second input; and

the outer codes include symbols from the pre-determined segments of the first data interleaved with symbols from pre-determined segments of the second data.

6. The apparatus of claim 5 further comprising:

the inner codewords include parity data calculated based on multiple pre-determined segments.

7. The apparatus of claim 5 further comprising:

the inner codewords include parity data calculated based on a single pre-determined segment.

8. The apparatus of claim 2 further comprising the pre-determined segments are less than all segments of the first data and the second data.

9. The apparatus of claim 8 comprising the circuit further configured to:

symbols from the pre-determined segments of the first data interleaved with symbols from pre-determined segments of the second data to produce the outer codes.

10. The apparatus of claim 2 comprising the circuit further configured to:

perform the error correction operation based on the inner codes; and

when the error correction operation does not converge, perform the error correction operation based on the outer codes.

11. The apparatus of claim 2 comprising the circuit further configured to:

iteratively decode between the inner codes and the outer codes; and

vary a calculation of the outer codes during the iterative decoding.

12. An apparatus comprising:

a data storage medium including;

a first data set stored in a first distinct area, and a second data set stored in a second distinct area;

inner codes and outer codes corresponding to a pre-determined combination of the first data set and the second data set;

a multi-dimensional recording system configured to access two or more memory groups of the data storage medium at approximately a same time; and

a coding circuit configured to receive data corresponding to the inner codes and outer codes of two memory groups to perform error correction operations on the first data set and the second data set.

13. The apparatus of claim 12 further comprising:

the data storage medium is a disc in a magnetic storage device;

the first distinct area is a first track on the disc and the second distinct area is a second track on the disc;

each track is logically divided into a pre-determined number of sectors, each of the sectors having a pre-determined number of symbols; and

at least one of the pre-determined sectors is a parity sector configured to store error correcting code (ECC).

14. The apparatus of claim 12 further comprising:

the coding circuit is further configured to perform error correction operations utilizing the inner codes from a pre-determined sector of the first distinct area and a pre-determined sector of the second distinct area; and

the inner codes include data to perform error correction operations from a pre-determined parity sector of the first distinct area and a pre-determined parity sector of the second distinct area.

15. The apparatus of claim 12 further comprising:

the outer codes are a combination of the symbols from the first distinct area and the symbols from the second distinct area.

16. The apparatus of claim 15 further comprising:

the outer codes are the symbols from a first track interleaved with the symbols from a second track of a disc data storage medium.

17. The apparatus of claim 14 further comprising:

the coding circuit is further configured to perform error correction operations utilizing the inner codes from a pre-determined sector of the first distinct area and second data to perform error correction operations from a pre-determined sector of the second distinct area; and

the outer codes are the symbols from the first distinct area interleaved with the symbols from the second distinct area.

18. The apparatus of claim 12 further comprising:

the outer codes contains a number of symbols from pre-determined sectors of the first distinct area track and the second distinct area; and

the pre-determined sectors are less than all of the first distinct area and the second distinct area.

19. A method comprising:

receiving first data from a first input, the first data including first segments of data, each segment of the first segments having multiple symbols;

receiving second data at a second input at approximately the same time as the first data is received at the first input, the second data including second segments of data, each segment of the second segments having multiple symbols;

determining inner codes and outer codes corresponding to the data; and

performing error correction operations on the data based on the inner codes and the outer codes.

20. The method of claim 19 further comprising:

when the data has at least one error, attempting to fix the at least one error by performing the error correction operations using inner codes corresponding to a segment having at least one error;

when the at least one error is not repaired by the performing error correction operations using the inner codes, performing error correction operations using the outer codes; and

when the at least one error is not repaired by the performing error correction operations using the outer codes, repairing the at least one error by iteratively performing error correction operations via the inner codes and the outer codes.