Storage control device and system to improve data retention in variable resistance memory cells

• US 9,396,132 B2
• Filed: 12/20/2012
• Issued: 07/19/2016
• Est. Priority Date: 01/12/2012
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Adachi, Naohiro, Tsutsui, Keiichi, Nakanishi, Kenichi, Okubo, Hideaki, Yamamoto, Makiko, Fujinami, Yasushi
• Primary Examiner(s): Nguyen, Than
• Application Number:
  US14/364,646
• Publication Number:
  US 20150234749A1
• Time in Patent Office: 1,307 Days
• Field of Search: 711/155, 365/148, 714/719
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2207/2263 Write conditionally, e.g. only if new data and old data differ
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 7/1009 Data masking during input/output

Abstract

Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data, a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value, a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell, and a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value.

Claims

1. A storage control device comprising:

a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data;

a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value;

a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell; and

a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value.

2. The storage control device according to claim 1,

wherein the memory cell is a variable resistance element,

wherein the first threshold value is set to a higher resistance state side than a standard threshold value, and

wherein the second threshold value is set to a lower resistance state side than the standard threshold value.

3. The storage control device according to claim 2

wherein the first value is a logical value 0, and

wherein the second value is a logical value 1.

4. The storage control device according to claim 1

wherein the memory cell is a variable resistance element,

wherein the first threshold value is set to a lower resistance state side than a standard threshold value, and

wherein the second threshold value is set to a higher resistance state side than the standard threshold value.

5. The storage control device according to claim 4

wherein the first value is a logical value 1, and

wherein the second value is a logical value 0.

6. A storage control device comprising:

an operation mode setting unit configured to set any one of a first mode or a second mode as an operation mode;

a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell in a case where the first mode is set, the data being read as first read data;

a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value in a case where the first mode is set;

a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell in a case where the first mode is set;

a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value in a case where the first mode is set;

a third read processing unit configured to read a third read data based on a standard threshold value in the memory cell in a case where the second mode is set; and

a third write processing unit configured to rewrite the memory cell to the first value when the write data is the first value and the third read data is the second value and configured to rewrite the memory cell to the second value when the write data is the second value and the third read data is the first value, in a case where the second mode is set.

7. The storage control device according to claim 6, wherein, if an error is detected and an error correction is performed on the detected error upon read processing, the first mode is set as the operation mode, an address for the error correction is set as the write address, and the error-corrected data is rewritten as the write data.

8. A storage device comprising:

a memory array configured to include a memory cell;

a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in the memory cell, the data being read as first read data;

a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value;

a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell; and

a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value.

9. A storage device comprising:

a memory array configured to include a memory cell;

an operation mode setting unit configured to set any one of a first mode or a second mode as an operation mode;

a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in the memory cell in a case where the first mode is set, the data being read as first read data;

a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value in a case where the first mode is set;

a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell in a case where the first mode is set;

a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value in a case where the first mode is set;

a third read processing unit configured to read a third read data based on a standard threshold value in the memory cell in a case where the second mode is set; and

a third write processing unit configured to rewrite the memory cell to the first value when the write data is the first value and the third read data is the second value and configured to rewrite the memory cell to the second value when the write data is the second value and the third read data is the first value, in a case where the second mode is set.

10. An information processing system comprising:

a memory array configured to include a memory cell;

an operation mode setting unit configured to set any one of a first mode or a second mode as an operation mode;

a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in the memory cell in a case where the first mode is set, the data being read as first read data;

a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value in a case where the first mode is set;

a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell in a case where the first mode is set;

a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value in a case where the first mode is set;

a third read processing unit configured to read a third read data based on a standard threshold value in the memory cell in a case where the second mode is set;

a third write processing unit configured to rewrite the memory cell to the first value when the write data is the first value and the third read data is the second value and configured to rewrite the memory cell to the second value when the write data is the second value and the third read data is the first value, in a case where the second mode is set; and

a host computer configured to issue a read command or a write command to the memory array.

11. The information processing system according to claim 10, wherein the host computer adds information about a rewriting frequency of write data according to the write command to the write command and issues the command, and

wherein the operation mode setting unit sets the first mode if the rewriting frequency of the write data indicates a low frequency, and sets the second mode if otherwise.

12. A storage controlling method comprising:

performing a first read process of reading data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data;

performing a first write process of rewriting the memory cell to the first value when write data is the first value and the first read data is the second value;

performing a second read process of reading second read data based on a second threshold value different from the first threshold value in the memory cell; and

performing a second write process of rewriting the memory cell to the second value when the write data is the second value and the second read data is the first value.