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Multi-core processor for managing data packets in communication network

  • US 9,396,154 B2
  • Filed: 04/22/2014
  • Issued: 07/19/2016
  • Est. Priority Date: 04/22/2014
  • Status: Active Grant
First Claim
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1. A system-on-chip (SoC) for processing data packets, the SOC comprising:

  • a plurality of cores;

    a data buffer for storing the data packets;

    a memory for storing a plurality of buffer descriptor rings, wherein each buffer descriptor ring includes a plurality of buffer descriptors, and a buffer descriptor corresponds to a data packet;

    a hardware accelerator that receives the data packets, associates each data packet with a corresponding buffer descriptor, and generates a first hardware signal when a first set of the data packets is stored in the data buffer; and

    an interrupt controller, connected to the hardware accelerator, the interrupt controller including a status table corresponding to the plurality of cores for selecting a first core of the plurality of cores, wherein the interrupt controller;

    selects the first core using the status table; and

    generates a first interrupt signal based on the first hardware signal and transmits the first interrupt signal to the first core,wherein the first core;

    creates a first virtual queue for storing a copy of a first set of buffer descriptors of a first buffer descriptor ring of the plurality of buffer descriptor rings that correspond to the first set of data packets, andindicates to the hardware accelerator that the first set of data packets is processed, andwherein the hardware accelerator generates a second hardware signal when a second set of the data packets is stored in the data buffer.

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