Multi-core processor for managing data packets in communication network

• US 9,396,154 B2
• Filed: 04/22/2014
• Issued: 07/19/2016
• Est. Priority Date: 04/22/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Garg, Vakul, Bhushan, Bharat
• Primary Examiner(s): Auve, Glenn A
• Application Number:
  US14/258,046
• Publication Number:
  US 20150301975A1
• Time in Patent Office: 819 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 63/0485 Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up

Abstract

A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.

Claims

1. A system-on-chip (SoC) for processing data packets, the SOC comprising:

a plurality of cores;

a data buffer for storing the data packets;

a memory for storing a plurality of buffer descriptor rings, wherein each buffer descriptor ring includes a plurality of buffer descriptors, and a buffer descriptor corresponds to a data packet;

a hardware accelerator that receives the data packets, associates each data packet with a corresponding buffer descriptor, and generates a first hardware signal when a first set of the data packets is stored in the data buffer; and

an interrupt controller, connected to the hardware accelerator, the interrupt controller including a status table corresponding to the plurality of cores for selecting a first core of the plurality of cores, wherein the interrupt controller;

selects the first core using the status table; and

generates a first interrupt signal based on the first hardware signal and transmits the first interrupt signal to the first core,

wherein the first core;

creates a first virtual queue for storing a copy of a first set of buffer descriptors of a first buffer descriptor ring of the plurality of buffer descriptor rings that correspond to the first set of data packets, and

indicates to the hardware accelerator that the first set of data packets is processed, and

wherein the hardware accelerator generates a second hardware signal when a second set of the data packets is stored in the data buffer.

2. The SoC of claim 1, wherein the interrupt controller further:

selects a second core of the plurality of cores using the status table;

generates a second interrupt signal based on the second hardware signal, and transmits the second interrupt signal to the second core,

wherein the second core;

creates a second virtual queue and stores a copy of a second set of buffer descriptors of the first buffer descriptor ring that corresponds to the second set of data packets; and

indicates to the hardware accelerator that the second set of data packets are processed.

3. The SoC of claim 2, wherein the first and second cores simultaneously process the first and second sets of data packets from the first and second virtual queues, respectively.

4. The SoC of claim 2, wherein the first and second cores include first and second interrupt service routines that mask the first and second interrupt signals, respectively, when the first and second cores create the copies of the first and second sets of buffer descriptors, respectively.

5. The SoC of claim 1, wherein the memory further includes a plurality of buffer descriptor ring index registers corresponding to the plurality of buffer descriptor rings, wherein the plurality of buffer descriptor ring index registers include corresponding producer and consumer index registers.

6. The SoC of claim 5, wherein the hardware accelerator increments a producer index register corresponding to a buffer descriptor ring when a data packet is associated to a corresponding buffer descriptor of the buffer descriptor ring.

7. The SoC of claim 5, wherein a core increments a consumer index register corresponding to a buffer descriptor ring when the core creates a copy of a buffer descriptor of the buffer descriptor ring in a virtual queue.

8. The SoC of claim 1, wherein the status table stores at least one of a busy and an idle status for each of the cores of the plurality of cores.

9. The SoC of claim 8, wherein the status table stores an idle status corresponding to the first core when the first core finishes processing the first set of data packets.

10. The SoC of claim 1, wherein the hardware accelerator comprises at least one of an Ethernet controller, a cryptographic accelerator, a pattern-matching accelerator, and a compression accelerator.

11. A method of processing a plurality of data packets in a system-on-chip (SoC) that includes a plurality of cores, a data buffer that stores the plurality of data packets, a memory that stores a plurality of buffer descriptor rings, wherein each buffer descriptor ring includes a plurality of buffer descriptors and a buffer descriptor corresponds to a data packet, the method comprising:

receiving the plurality of data packets;

generating a first hardware signal when a first set of data packets of the plurality of data packets are stored in the data buffer;

selecting a first core of the plurality of cores;

creating a copy of a first set of buffer descriptors of a first buffer descriptor ring of the plurality of buffer descriptor rings corresponding to the first set of data packets in a first virtual queue of the first core;

indicating that the first set of data packets is processed; and

generating a second hardware signal when a second set of data packets of the plurality of data packets are stored in the data buffer.

12. The method of claim 11, further comprising:

selecting a second core of the plurality of cores;

creating a copy of a second set of buffer descriptors of the first buffer descriptor ring corresponding to the second set of data packets in a second virtual queue of the second core; and

indicating that the second set of data packets is processed.

13. The method of claim 11, wherein the memory further stores a plurality of buffer descriptor ring index registers, corresponding to the plurality of buffer descriptor rings, that include corresponding producer and consumer index registers.

14. The method of claim 13, further comprising incrementing a producer index register corresponding to a buffer descriptor ring when a data packet is associated to a corresponding buffer descriptor of the buffer descriptor ring.

15. The method of claim 13, further comprising incrementing a consumer index register corresponding to a buffer descriptor ring when a core creates a copy of a buffer descriptor of the buffer descriptor ring in a virtual queue thereof.

16. A method of processing a plurality of data packets in a system-on-chip (SoC) that includes a plurality of cores, a data buffer that stores the plurality of data packets, a memory that stores a plurality of buffer descriptor rings, wherein each buffer descriptor ring includes a plurality of buffer descriptors and a buffer descriptor corresponds to a data packet, the method comprising:

receiving the plurality of data packets;

generating a first hardware signal when a first set of data packets of the plurality of data packets are stored in the data buffer;

selecting a first core of the plurality of cores;

creating a copy of a first set of buffer descriptors of a first buffer descriptor ring of the plurality of buffer descriptor rings corresponding to the first set of data packets in a first virtual queue of the first core;

indicating that the first set of data packets is processed;

generating a second hardware signal when a second set of data packets of the plurality of data packets are stored in the data buffer;

selecting a second core of the plurality of cores;

creating a copy of a second set of buffer descriptors of the first buffer descriptor ring corresponding to the second set of data packets in a second virtual queue of the second core;

indicating that the second set of data packets is processed; and

processing the first and second sets of data packets, simultaneously, by the first and second cores, respectively.

17. The method of claim 16, wherein the memory further stores a plurality of buffer descriptor ring index registers, corresponding to the plurality of buffer descriptor rings, that include corresponding producer and consumer index registers.

18. The method of claim 17, further comprising incrementing a producer index register corresponding to a buffer descriptor ring when a data packet is associated to a corresponding buffer descriptor of the buffer descriptor ring.

19. The method of claim 17, further comprising incrementing a consumer index register corresponding to a buffer descriptor ring when a core creates a copy of a buffer descriptor of the buffer descriptor ring in a virtual queue thereof.