Method, system, and computer program product for interconnecting circuit components with track patterns for electronic circuit designs

• US 9,396,301 B1
• Filed: 05/30/2014
• Issued: 07/19/2016
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Lee, Yinnie, Markham, Jeffrey, Ruehl, Roland, Sharma, Karun
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US14/292,166
• Time in Patent Office: 781 Days
• Field of Search: 716/112, 716/126, 716/129, 716/130
• US Class Current: 1/1
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.

Claims

1. A computer implemented method for interconnecting circuit components with track patterns for electronic designs, comprising:

identifying an electronic design including a source pin and a destination pin;

identifying or determining a transition pattern for interconnecting the source pin and destination pin at least by selecting multiple routing tracks from one or more track patterns, wherein

the one or more track patterns respectively correspond to one or more legal combinations of widths that are arranged in one or more predetermined permissible sequences and are associated with the multiple routing tracks, and a routing track in the multiple routing tracks has zero-width; and

interconnecting, at one or more track pattern modules stored at least partially in memory and including or functioning in conjunction with at least one processor in a computing system, the source pin and the destination pin based at least in part upon the transition pattern.

2. The computer implemented method of claim 1, the act of identifying the electronic design comprising:

identifying the source pin on a first routing track and the destination pin on a second routing track;

identifying a set of design rules governing implementation of the electronic design; and

identifying or determining an ordering of interconnections.

3. The computer implemented method of claim 2, the act of identifying the electronic design further comprising:

identifying or determining a dependency relation between the source pin and the destination pin; and

identifying one or more characteristics associated with the first routing track and the second routing track, wherein

the one or more characteristics include a first width of the source pin and a second width of the destination pin, and

the one or more characteristics are used to determine a width of a transition segment for interconnecting the source pin and the destination pin with the transition pattern.

4. The computer implemented method of claim 1, the act of identifying or determining the transition pattern comprising:

identifying the source pin along a first routing track and the destination along a second routing track in a first routing direction;

identifying or determining one or more characteristics of the transition pattern, wherein the one or more characteristics include a first width associated with the first routing track or the second width associated with the routing second track;

identifying a third routing track in a second routing direction for the transition pattern; and

identifying a dummy routing track for the first routing track or the second routing track.

5. The computer implemented method of claim 4, the act of identifying or determining the transition pattern further comprising:

identifying one or more neighboring routing tracks of the dummy routing track;

determining whether or not the dummy routing track, when inserted or arranged at a location, satisfies design rules governing routing tracks and track patterns; and

inserting the dummy routing track at the location when the dummy routing track is determined to satisfy the design rules.

6. The computer implemented method of claim 5, the act of identifying or determining the transition pattern further comprising:

identifying or creating a dummy pin along the dummy routing track; and

generating the transition pattern using at least the dummy pin, the dummy routing track, and the third routing track.

7. The computer implemented method of claim 1, the act of interconnecting the source pin and the destination pin comprising:

identifying the source pin along a first routing track and the destination pin along a second routing track in a first routing direction;

creating a wire segment along a third routing track in a second routing direction based at least in part upon the transition pattern and a set of design rules;

creating one or more wire segments in the first routing direction based at least in part upon the transition pattern and the set of design rules; and

creating an interconnection between the source pin and the destination pin with one or more bends by using the wire segment in the second routing direction and the one or more wire segments in the first routing direction.

8. The computer implemented method of claim 1, the act of interconnecting the source pin and the destination pin comprising:

identifying the source pin along a first routing track, the destination pin along a second routing track in a first routing direction on a first routing layer, and a third routing track along a second routing direction on a second routing layer;

identifying one or more via insertion locations and one or more via design rules governing implementation of vias in the electronic design;

ensuring the one or more via insertion locations satisfy the one or more via design rules; and

creating one or more vias at the one or more via insertion location based at least in part upon a result of ensuring the one or more via insertion locations satisfy the one or more via design rules.

9. The computer implemented method of claim 8, the act of interconnecting the source pin and the destination pin comprising:

creating one or more first wire segments in the first routing direction on the first routing layer based at least in part upon the transition pattern and the one or more via insertion locations;

creating a second wire segment in the second routing direction on the second routing layer based at least in part upon the transition pattern and the one or more via insertion locations; and

determining whether the one or more first wire segments or the second wire segment is design rule check clean.

10. The computer implemented method of claim 1, the process further comprising:

compacting the electronic design by modifying at least one location of a shape to another location.

11. The computer implemented method of claim 10, the process further comprising:

identifying a first shape along a first routing track associated with a first width and a second shape along a second routing track associated with a second width in a layout of the electronic design, wherein the first width is larger than the second width;

determining whether placing the first shape and the second shape on a same routing track satisfies a first set of design rules;

moving the second shape on the second routing track to the first routing track; and

reconfiguring the electronic design based at least in part upon a result of moving the second shape.

12. The computer implemented method of claim 11, the process further comprising:

determining whether a first length of the first shape or a second length of the second shape is modifiable; and

determining whether the electronic design including the second shape that has been moved to the first routing track satisfies a second set of design rules.

13. A system for interconnecting circuit components with track patterns for electronic designs, comprising:

a computer system including at least one processor or processor core that executes a sequence of instructions to;

identify an electronic design including a source pin and a destination pin;

identify or determine a transition pattern for interconnecting the source pin and destination pin at least by selecting multiple routing tracks from one or more track patterns, wherein

the one or more track patterns respectively correspond to one or more legal combinations of widths that are arranged in one or more corresponding permissible orders and are associated with the multiple routing tracks, and a routing track in the multiple routing tracks has zero-width; and

one or more track pattern modules stored at least partially in memory and including or functioning in conjunction with at least one processor or processor core to interconnect the source pin and the destination pin based at least in part upon the transition pattern.

14. The system of claim 13, wherein the at least one processor or processor core that executes a sequence of instructions to identify the electronic design further executes:

a first sequence of instructions to;

identify the source pin on a first routing track and the destination pin on a second routing track;

identify or determine an ordering of interconnections; and

identify or determine a dependency relation between the source pin and the destination pin;

or

a second sequence of instructions to;

identify the source pin along the first routing track and the destination along the second routing track in a first routing direction; and

identify a third routing track in a second routing direction for the transition pattern and a dummy routing track for the first routing track or the second routing track.

15. The system of claim 14, wherein the at least one processor or processor core that executes a sequence of instructions to identify or determining the transition pattern further executes the sequence of instructions to:

determine whether or not the dummy routing track, when inserted or arranged at a location, satisfies design rules governing routing tracks and track patterns based at least in part upon one or more neighboring routing tracks of the dummy routing track;

insert the dummy routing track at the location when the dummy routing track is determined to satisfy the design rules;

identify or create a dummy pin along the dummy routing track; and

generate the transition pattern using at least the dummy pin, the dummy routing track, and the third routing track.

16. The system of claim 13, wherein the at least one processor or processor core that executes a sequence of instructions to interconnect the source pin and the destination pin further executes the sequence of instructions to:

a first sequence of instructions to;

identify the source pin along a first track and the destination pin along a second routing track in a first routing direction;

create a wire segment along a third routing track in a second routing direction based at least in part upon the transition pattern and a set of design rules;

create one or more wire segments in the first routing direction based at least in part upon the transition pattern and the set of design rules; and

create an interconnection between the source pin and the destination pin with one or more bends by using the wire segment in the second routing direction and the one or more wire segments in the first routing direction;

a second sequence of instructions to;

identify the source pin along the first routing track, the destination pin along the second routing track in a first routing direction on a first routing layer, and the third routing track along a second routing direction on a second routing layer;

identify one or more via insertion locations and one or more via design rules governing implementation of vias in the electronic design; and

create one or more vias at the one or more via insertion location based at least in part upon a result of ensuring the one or more via insertion locations satisfy the one or more via design rules;

or

a third sequence of instructions to;

compact the electronic design, comprising;

identify a first shape along the first routing track associated with the first width and a second shape along the second track associated with a second width in a layout of the electronic design, wherein the first width is larger than the second width;

determine whether placing the first shape and the second shape on a same routing track satisfies a first set of design rules;

move the second shape on the second routing track to the first routing track; and

reconfigure the electronic design based at least in part upon a result of moving the second shape.

17. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one customizable processor executing one or more threads, causes the at least one customizable processor to perform a method for interconnecting circuit components with track patterns for electronic designs, the method comprising:

identifying an electronic design including a source pin and a destination pin;

identifying or determining a transition pattern for interconnecting the source pin and destination pin at least by selecting multiple routing tracks from one or more track patterns, wherein

the one or more track patterns respectively correspond to one or more legal combinations of widths arranged in one or more corresponding permissible orders that are arranged in one or more predetermined permissible sequences and are associated with the multiple routing tracks, and a routing track in the multiple routing tracks has zero-width; and

interconnecting, at one or more track pattern modules stored at least partially in memory and including or functioning in conjunction with at least one processor in the computing system, the source pin and the destination pin based at least in part upon the transition pattern.

18. The article of manufacture of claim 17, the act of identifying the electronic design comprising:

a first set of actions including;

identifying the source pin on a first routing track and the destination pin on a second routing track;

identifying or determining an ordering of interconnections; and

identifying or determining a dependency relation between the source pin and the destination pin;

or

a second set of actions including;

identifying the source pin along the first routing track and the destination along the second routing track in a first routing direction; and

identifying a third routing track in a second routing direction for the transition pattern and a dummy routing track for the first routing track or the second routing track.

19. The article of manufacture of claim 18, the act of identifying or determining the transition pattern further comprising:

determining whether or not the dummy routing track, when inserted or arranged at a location, satisfies design rules governing routing tracks and track patterns based at least in part upon one or more neighboring routing tracks of the dummy routing track;

inserting the dummy routing track at the location when the dummy routing track is determined to satisfy the design rules;

identifying or creating a dummy pin along the dummy routing track; and

generating the transition pattern using at least the dummy pin, the dummy routing track, and the third routing track.

20. The article of manufacture of claim 17, the act of interconnecting the source pin and the destination pin comprising:

a first set of actions including;

identifying the source pin along a first routing track and the destination pin along a second routing track in a first routing direction;

creating a wire segment along a third routing track in a second routing direction based at least in part upon the transition pattern and a set of design rules;

creating one or more wire segments in the first routing direction based at least in part upon the transition pattern and the set of design rules; and

creating an interconnection between the source pin and the destination pin with one or more bends by using the wire segment in the second routing direction and the one or more wire segments in the first routing direction;

a second set of actions including;

identifying the source pin along the first routing track, the destination pin along the second routing track in a first routing direction on a first routing layer, and a third routing track along a second routing direction on a second routing layer;

identifying one or more via insertion locations and one or more via design rules governing implementation of vias in the electronic design; and

creating one or more vias at the one or more via insertion location based at least in part upon a result of ensuring the one or more via insertion locations satisfy the one or more via design rules;

or

a third set of actions including;

compacting the electronic design, comprising;

identifying a first shape along the first routing track associated with a first width and a second shape along the second routing track associated with a second width in a layout of the electronic design, wherein the first width is larger than the second width;

determining whether placing the first shape and the second shape on a same routing track satisfies a first set of design rules;

moving the second shape on the second routing track to the first routing track; and

reconfiguring the electronic design based at least in part upon a result of moving the second shape.