Discrete three-dimensional memory

• US 9,396,764 B2
• Filed: 10/15/2015
• Issued: 07/19/2016
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US14/884,755
• Publication Number:
  US 20160035394A1
• Time in Patent Office: 278 Days
• Field of Search: 257/296, 257/303, 257/311, 257/314, 257/315, 257/686, 438/238, 438/241, 438/257, 438/258, 438/262, 438/264, 438/266
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

Claims

1. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising at least a 3D-M array, wherein said 3D-M array comprises a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M array, wherein said off-die peripheral-circuit component is absent from said 3D-array die;

means for coupling said 3D-array die and said peripheral-circuit die;

wherein the number of address-line levels in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; and

, said 3D-array die and said peripheral-circuit die are separate dice.

2. The memory according to claim 1, wherein said 3D-M is a three-dimensional read-only memory (3D-ROM), or a three-dimensional random-access memory (3D-RAM).

3. The memory according to claim 1, wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.

4. The memory according to claim 1, further comprising another 3D-array die including at least another 3D-M array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.

5. The memory according to claim 1, wherein said off-die peripheral-circuit component is a read-voltage generator and/or a write-voltage generator.

6. The memory according to claim 1, wherein said off-die peripheral-circuit component is an address translator and/or a data translator.

7. A discrete three-dimensional memory (3D-M), comprising:

a 3D-array die comprising at least a 3D-M array, wherein said 3D-M array comprises a plurality of vertically stacked memory levels;

a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M array, wherein said off-die peripheral-circuit component is absent from said 3D-array die;

means for coupling said 3D-array die and said peripheral-circuit die;

wherein the number of interconnect levels in said peripheral-circuit die is more than the number of interconnect levels in said 3D-array die, but substantially less than the number of address-line levels in said 3D-array die; and

, said 3D-array die and said peripheral-circuit die are separate dice.

8. The memory according to claim 7, wherein said 3D-M is a three-dimensional read-only memory (3D-ROM), or a three-dimensional random-access memory (3D-RAM).

9. The memory according to claim 7, wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.

10. The memory according to claim 7, further comprising another 3D-array die including at least another 3D-M array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.

11. The memory according to claim 7, wherein said off-die peripheral-circuit component is a read-voltage generator and/or a write-voltage generator.

12. The memory according to claim 7, wherein said off-die peripheral-circuit component is an address translator and/or a data translator.