Semiconductor device
First Claim
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1. A semiconductor device comprising:
- a first cell array region disposed adjacent to a second cell array region;
a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines;
first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines;
second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines;
first input/output switching units electrically coupling a first group of the dummy bit lines and bit lines of the first cell array region with the first group segment input/output lines;
second input/output switching units electrically coupling a second group of the dummy bit lines and bit lines of the second cell array with the second group segment input/output lines; and
switching units configured to electrically couple the first group segment input/output lines or the second group segment input/output lines with local input/output lines in response to a switching signal,wherein the first input/output switching units and the second input/output switching units configured to switch in response to a same column select signal.
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Abstract
A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines.
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Citations
18 Claims
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1. A semiconductor device comprising:
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a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines; first input/output switching units electrically coupling a first group of the dummy bit lines and bit lines of the first cell array region with the first group segment input/output lines; second input/output switching units electrically coupling a second group of the dummy bit lines and bit lines of the second cell array with the second group segment input/output lines; and switching units configured to electrically couple the first group segment input/output lines or the second group segment input/output lines with local input/output lines in response to a switching signal, wherein the first input/output switching units and the second input/output switching units configured to switch in response to a same column select signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17)
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13. A semiconductor device comprising:
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a plurality of cell array regions including a plurality of memory cells; a dummy cell region disposed between a first cell array region which is any one of the plurality of cell array regions and a second cell array region disposed adjacent to the first cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines; a plurality of bit line sense amplifiers configured to amplify data applied from the plurality of cell array regions and data applied from the dummy bit lines; first input/output switching units electrically coupling a first group of the dummy bit lines and bit lines of the first cell array region with the first group segment input/output lines; second input/output switching units electrically coupling a second group of the dummy bit lines and bit lines of the second cell array with the second group segment input/output lines; and switching units configured switching units configured to electrically couple the first group segment input/output lines or the second group segment input/output lines with local input/output lines in response to a switching signal, wherein the first input/output switching units and the second input/output switching units configured to switch in response to a same column select signal. - View Dependent Claims (14, 15, 16, 18)
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Specification