Memory operations using system thermal sensor data

• US 9,396,787 B2
• Filed: 12/23/2011
• Issued: 07/19/2016
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Shoemaker, Kenneth, Fahey, Paul
• Primary Examiner(s): Lam, David
• Application Number:
  US13/997,975
• Publication Number:
  US 20140140156A1
• Time in Patent Office: 1,670 Days
• Field of Search: 365/211, 365/222, 365/201, 365/61
• US Class Current: 1/1
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

Claims

1. A memory device comprising:

a memory stack including one or more coupled memory elements; and

a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip;

wherein the memory controller is to obtain thermal values of the one or more thermal sensors, the logic chip to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic chip; and

wherein a refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

2. The memory device of claim 1, wherein the memory controller is to modify the refresh rate for the one or more portions of the memory stack based at least in part on the estimated thermal conditions for the memory stack.

3. The memory device of claim 2, wherein the memory controller is to modify the refresh rate by instructing a memory element regarding a refresh rate for the memory element.

4. The memory device of claim 2, wherein the memory controller is to modify the refresh rate by running one or more refresh cycles for the memory element at a time when the memory element is not itself running a refresh cycle.

5. The memory device of claim 1, wherein the memory device is to provide data regarding the estimated thermal conditions for the memory stack to a memory element of the memory stack, the memory element to modify the refresh rate for the memory element using the estimated thermal conditions.

6. The memory device of claim 1, wherein the refresh rate is further based on memory performance data for the memory stack.

7. The memory device of claim 1, wherein the logic chip is a system on chip (SoC).

8. The memory device of claim 1, wherein the one or more memory elements are dynamic random-access memory (DRAM) elements.

9. The memory device of claim 1, wherein the one or more memory elements do not include thermal sensors.

10. The memory device of claim 1, wherein the one or more memory elements include thermal sensors that are not accessible to the memory controller.

11. The memory device of claim 1, wherein the one or more memory elements include thermal sensors, and wherein the memory elements use the estimated thermal conditions to tune temperature values generated by the thermal sensors of the memory elements.

12. The memory device of claim 1, wherein the memory elements include one of a plurality of memory die layers or a plurality of memory packages.

13. A method comprising:

collecting temperature data from one or more thermal sensors in a logic chip, the logic chip being coupled with a memory stack;

estimating thermal conditions of the memory stack based on the collected temperature data and a location of each of the one or more thermal sensors;

determining a recommended refresh rate for each of one or more portions of the memory stack; and

upon determining that a refresh rate of a portion of the memory stack is different than a recommended refresh rate, adjusting the refresh rate for the portion of the memory stack.

14. The method of claim 13, wherein adjusting the refresh rate includes a memory controller of the logic chip to adjust the refresh rate for the one or more portions of the memory stack based at least in part on the estimated thermal conditions for the memory stack.

15. The method of claim 14, wherein the memory controller is to adjust the refresh rate by:

instructing a memory element regarding a refresh rate for the memory element;

or

running one or more refresh cycles for the memory element at a time when the memory element is not itself running a refresh cycle.

16. The method of claim 13, further comprising providing by the memory device data regarding the estimated thermal conditions to a memory element of the memory stack, wherein adjusting the refresh rate includes the memory element to adjust the refresh rate for the memory element using the estimated thermal conditions.

17. The method of claim 13, wherein the refresh rate is further based on memory performance data for the memory stack.

18. The method of claim 13, wherein the memory elements do not include thermal sensors.

19. The method of claim 13, wherein the memory elements include thermal sensors that are not accessible to a memory controller.

20. The method of claim 13, wherein the one or more memory elements include thermal sensors, and further comprising the memory elements using the estimated thermal conditions to tune temperature values generated by the thermal sensors of the memory elements.

21. A system comprising:

a processor to process data of the system;

a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both; and

a memory to store data, the memory including a stacked memory device, the stacked memory device including;

a memory stack including one or more coupled memory elements; and

a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip;

wherein the memory controller to obtain thermal values of the one or more thermal sensors, the logic chip to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic chip; and

wherein a refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

22. The system of claim 21, wherein the memory controller is to modify the refresh rate for the one or more portions of the memory stack based at least in part on the estimated thermal conditions for the memory stack.

23. The system of claim 22, wherein the memory controller is to modify the refresh rate by:

instructing a memory element regarding a refresh rate for the memory element;

or

running one or more refresh cycles for the memory element at a time when the memory element is not itself running a refresh cycle.

24. The system of claim 21, wherein the memory device is to provide data regarding the estimated thermal conditions for the memory stack to a memory element of the memory stack, the memory element to modify the refresh rate for the memory element using the estimated thermal conditions.

25. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:

collecting temperature data from one or more thermal sensors in a logic chip, the logic chip being coupled with a memory stack;

estimating thermal conditions of the memory stack based on the collected temperature data and a location of each of the one or more thermal sensors;

determining a recommended refresh rate for each of one or more portions of the memory stack; and

upon determining that a refresh rate of a portion of the memory stack is different than a recommended refresh rate, adjusting the refresh rate for the portion of the memory stack.

26. The medium of claim 25, wherein adjusting the refresh rate includes a memory controller of the logic chip to adjust the refresh rate for the one or more portions of the memory stack based at least in part on the estimated thermal conditions for the memory stack.

27. The medium of claim 26, wherein the memory controller is to adjust the refresh rate by:

instructing a memory element regarding a refresh rate for the memory element;

or

running one or more refresh cycles for the memory element at a time when the memory element is not itself running a refresh cycle.

28. The medium of claim 25, further comprising further comprising instructions that, when executed by the processor, cause the processor to perform operations comprising:

providing by the memory device data regarding the estimated thermal conditions to a memory element of the memory stack, wherein adjusting the refresh rate includes the memory element to adjust the refresh rate for the memory element using the estimated thermal conditions.