Pulse signal output circuit and shift register
First Claim
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1. A semiconductor device comprising:
- a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor,wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor,wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor,wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the first transistor,wherein a first signal is input to the other of source and drain of the first transistor,wherein a first potential is input to the other of source and drain of the second transistor, andwherein a second signal is output from the one of source and drain of the first transistor.
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Abstract
An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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Citations
15 Claims
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1. A semiconductor device comprising:
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a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor, wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor, wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor, wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the first transistor, wherein a first signal is input to the other of source and drain of the first transistor, wherein a first potential is input to the other of source and drain of the second transistor, and wherein a second signal is output from the one of source and drain of the first transistor. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device comprising:
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a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor, wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor, wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor, wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the first transistor, wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the third transistor, wherein a first signal is input to the other of source and drain of the first transistor, wherein a first potential is input to the other of source and drain of the second transistor, and wherein a second signal is output from the one of source and drain of the first transistor. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor device comprising:
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a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor, wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor, wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor, wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor, wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the third transistor, wherein a first signal is input to the other of source and drain of the first transistor, wherein a first potential is input to the other of source and drain of the second transistor, and wherein a second signal is output from the one of source and drain of the first transistor. - View Dependent Claims (12, 13, 14, 15)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsAmano, Seiko, Toyotaka, Kouhei, Miyake, Hiroyuki, Miyazaki, Aya, Shishido, Hideaki, Kusunoki, Koji
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Primary Examiner(s)Lam, Tuan T
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Application NumberUS14/245,097Publication NumberTime in Patent Office837 DaysField of SearchNoneUS Class Current1/1CPC Class CodesG09G 2300/0809 Several active elements per...G09G 2310/0286 Details of a shift register...G09G 3/3677 suitable for active matrice...G09G 3/3696 Generation of voltages supp...G11C 19/184 with field-effect transisto...G11C 19/28 using semiconductor element...H01L 25/03 all the devices being of a ...H01L 27/1222 with a particular compositi...H01L 27/1225 with semiconductor material...H01L 27/124 with a particular compositi...H01L 27/1251 comprising TFTs having a di...H01L 27/127 with a particular formation...H01L 27/1288 employing particular maskin...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...H03K 19/0013 in field effect transistor ...H05K 7/02 Arrangements of circuit com...
