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Memory structure

  • US 9,396,815 B2
  • Filed: 05/07/2014
  • Issued: 07/19/2016
  • Est. Priority Date: 08/12/2009
  • Status: Active Grant
First Claim
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1. A memory structure comprising:

  • a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;

    a plurality of first bits, each first bit of the plurality of first bits being associated with a memory word of the plurality of memory words, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;

    a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words being associated with a corresponding memory word of the plurality of memory words; and

    a plurality of second bits, each second bit of the plurality of second bits being associated with a redundancy word of the plurality of redundancy words, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit.

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