Memory structure
First Claim
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1. A memory structure comprising:
- a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;
a plurality of first bits, each first bit of the plurality of first bits being associated with a memory word of the plurality of memory words, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;
a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words being associated with a corresponding memory word of the plurality of memory words; and
a plurality of second bits, each second bit of the plurality of second bits being associated with a redundancy word of the plurality of redundancy words, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit.
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Abstract
A memory structure includes a memory row of a memory array, a plurality of first bits, a first redundancy row, and a plurality of second bits. The memory row includes a plurality of memory words. The plurality of first bits is configured to indicate whether an individual memory word of the plurality of memory words of the memory row has an error. The first redundancy row includes a plurality of first redundancy words. The plurality of second bits is configured to indicate whether an individual first redundancy word of the plurality of first redundancy words of the first redundancy row has an error.
16 Citations
20 Claims
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1. A memory structure comprising:
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a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words; a plurality of first bits, each first bit of the plurality of first bits being associated with a memory word of the plurality of memory words, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit; a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words being associated with a corresponding memory word of the plurality of memory words; and a plurality of second bits, each second bit of the plurality of second bits being associated with a redundancy word of the plurality of redundancy words, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory structure comprising:
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a memory row of a memory array, the memory row including a plurality of memory words; a plurality of first bits configured to indicate whether an individual memory word of the plurality of memory words of the memory row has an error; a first redundancy row of the memory array, the first redundancy row including a plurality of first redundancy words; and a plurality of second bits configured to indicate whether an individual first redundancy word of the plurality of first redundancy words of the first redundancy row has an error. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method comprising:
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accessing data stored in a memory word; determining, by an error correction engine, if the data contains an error; and in response to a determination that the data contains the error; updating a tag logic value associated with the memory word to indicate that the memory word has at least one failed bit; and generating an error-fixing flag when the tag logic value indicates that the memory word has at least one failed bit. - View Dependent Claims (17, 18, 19, 20)
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Specification