Self-repairing memory and method of use

• US 9,396,817 B2
• Filed: 04/30/2015
• Issued: 07/19/2016
• Est. Priority Date: 08/12/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: O'Connell, Cormac Michael
• Primary Examiner(s): Yang, Han
• Application Number:
  US14/700,861
• Publication Number:
  US 20150235716A1
• Time in Patent Office: 446 Days
• Field of Search: 365/200, 365/201, 365/230.02, 365/185.09
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A self-repair unit includes a self-repair address comparator configured to receive address information from a control logic circuit, and to compare the received address with a faulty address in a memory array. The self-repair unit further includes a redundant engine configured to re-direct access to a redundancy address in a redundant memory if the received address matches the faulty address, wherein the redundancy address corresponds to the faulty address in the memory array. The self-repair unit further includes a cache stack counter configured to determine a number of pending repairs in a corrected data cache connected to the memory array and to the redundant memory.

Claims

1. A self-repair unit comprising:

a self-repair address comparator configured to receive address information from a control logic circuit, and to compare the received address with a faulty address in a memory array;

a redundant engine configured to re-direct access to a redundancy address in a redundant memory if the received address matches the faulty address, wherein the redundancy address corresponds to the faulty address in the memory array; and

a cache stack counter configured to determine a number of pending repairs in a corrected data cache connected to the memory array and to the redundant memory.

2. The self-repair unit of claim 1, wherein the redundant engine is further configured to direct access to the received address if the received address is different from the faulty address.

3. The self-repair unit of claim 1, wherein the self-repair address comparator is further configured to determine whether the received address corresponds to a pending repair in the corrected data cache.

4. The self-repair unit of claim 1, wherein the redundant engine is configured to update error addresses in the self-repair address comparator, wherein the faulty address is one of the error addresses.

5. The self-repair unit of claim 1, wherein the cache stack counter is further configured to output a cache full signal if the number of pending repairs matches a capacity of the corrected data cache.

6. The self-repair unit of claim 1, wherein the cache stack counter is further configured to output a warning signal if the number of pending repairs is within a threshold number from a capacity of the corrected data cache.

7. The self-repair unit of claim 1, wherein the redundant engine is configured to reset a repeat error flag for the redundant address if the faulty address in the memory array is corrected in the redundant memory.

8. A method of using a memory, the method comprising:

detecting an error in a memory array;

correcting data corresponding to the detected error;

storing the corrected data in a corrected data cache;

monitoring a number of pending corrections stored in the corrected data cache; and

writing the stored corrected data to the memory array or to a redundant memory during a no-operation cycle.

9. The method of claim 8, further comprising outputting a cache full signal if the number of pending corrections matches a capacity of the corrected data cache.

10. The method of claim 9, further comprising providing the no-operation cycle in response to the cache full signal.

11. The method of claim 8, further comprising outputting a warning signal if the number of pending corrections is within a threshold number from a capacity of the corrected data cache.

12. The method of claim 8, wherein writing the stored corrected data comprises writing the stored corrected data to the memory array if the detected error is a soft error.

13. The method of claim 8, wherein writing the stored corrected data comprises writing the stored corrected data to the redundant memory if the detected error is a hard error.

14. The method of claim 8, further comprising identifying a write operation to an address of the detected error as the no-operation.

15. The method of claim 8, further comprising identifying a refresh process as the no-operation.

16. The method of claim 8, further comprising identifying a read operation of an address of the detected error as the no-operation.

17. A method of using a memory, the method comprising:

receiving an address of a memory cell of a memory array from a control circuit;

comparing the received address with an address of a pending repair in a corrected data cache, wherein the corrected data cache is configured to store corrected data based on detected errors;

writing the stored corrected data to the memory array or to a redundant memory if the received address matches the address of the pending repair; and

comparing a number of pending repairs in the corrected data cache with a capacity of the corrected data cache.

18. The method of claim 17, further comprising outputting a cache full signal if the number of pending corrections matches a capacity of the corrected data cache.

19. The method of claim 17, further comprising outputting a warning signal if the number of pending corrections is within a threshold number from a capacity of the corrected data cache.

20. The method of claim 17, further comprising writing the stored corrected data to the memory array or to the redundant memory during a no-operation cycle of the memory array.