Multilayered contact structure having nickel, copper, and nickel-iron layers

• US 9,396,991 B2
• Filed: 08/25/2014
• Issued: 07/19/2016
• Est. Priority Date: 08/25/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Arvin, Charles L., Cox, Harry D., Perfecto, Eric D., Wassick, Thomas A.
• Primary Examiner(s): PARENDO, KEVIN A
• Application Number:
  US14/467,191
• Publication Number:
  US 20160056072A1
• Time in Patent Office: 694 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03849 Reflowing
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0566 Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/10145 Flow barriers
• CPC Class Codes: H01L 2224/1146 : Plating
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13005 : Structure
• CPC Class Codes: H01L 2224/13006 : Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 : in side view
• CPC Class Codes: H01L 2224/1308 : being stacked
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1316 : Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01026 : Iron [Fe]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Claims

1. A semiconductor device fabrication method comprising:

forming a barrier layer upon a dielectric layer;

forming an electrically conductive plating layer upon the barrier layer, and;

forming a multilayered contact upon the plating layer by plating a first Nickel layer upon the plating layer, plating a Copper layer upon the first Nickel layer, plating a second Nickel layer upon the Copper layer, and plating a Nickel-Iron layer upon the second Nickel layer,

wherein the barrier layer is a first thickness;

the plating layer is a second thickness; and

each of the first Nickel layer, the Copper layer, the second Nickel layer, and the Nickel-Iron layer is a third thickness different than the first thickness and the second thickness.

2. The semiconductor device fabrication method of claim 1, further comprising:

attaching a handler wafer to the multilayered contact side of the semiconductor device with adhesive.

3. The semiconductor device fabrication method of claim 1, further comprising:

forming a photoresis upon the conductive layer;

forming an contact trench in the photoresist layer, the contact trench exposing a portion of the plating layer;

forming the multilayered contact structure within the contact trench, and;

removing the photoresist.

4. The semiconductor device fabrication method of claim 1, further comprising:

removing portions of the conductive layer exterior to the multilayered contact structure, such that sidewalls of the conductive layer are coplanar with sidewalls a particular layer of the multilayered contact.

5. The semiconductor device fabrication method of claim 1, further comprising:

removing portions of the barrier layer exterior to the multilayered contact structure, such that sidewalls of the barrier layer are coplanar with sidewalls a particular layer of the multilayered contact.

6. The semiconductor device fabrication method of claim 1, wherein the semiconductor device is a thinned die and wherein at least one layer of the multilayer contact is wettable to solder electrically connected a second die in a three dimensional package.

7. The semiconductor device fabrication method of claim 1, wherein the Nickel-Iron layer is a topmost layer of the multilayered contact.

8. The semiconductor device fabrication method of claim 7, further comprising applying solder to a top surface of the Nickel-Iron layer.

9. The semiconductor device fabrication method of claim 1, further comprising:

forming the dielectric layer upon a substrate;

forming a metal line in the dielectric layer; and

forming a via between and contacting the metal line and the barrier layer.

10. The semiconductor device fabrication method of claim 1, wherein sidewalls of the barrier layer, the plating layer, the first Nickel layer, the Copper layer, the second Nickel layer, and the Nickel-Iron layer are all coplanar.

11. A semiconductor device fabrication method comprising:

forming a barrier layer upon a dielectric layer;

forming an electrically conductive plating layer upon the barrier layer, and;

forming a multilayered contact upon the plating layer, the multilayered contact comprising;

a first Nickel layer upon the plating layer, a Copper layer upon the first Nickel layer, a second Nickel layer upon the Copper layer, and a Nickel-Iron layer upon the second Nickel layer,

wherein the barrier layer is a first thickness;

the plating layer is a second thickness; and

each of the first Nickel layer, the Copper layer, the second Nickel layer, and the Nickel-Iron layer is a third thickness different than the first thickness and the second thickness.

12. The semiconductor device fabrication method of claim 11, wherein the Nickel-Iron layer is a topmost layer of the multilayered contact.

13. The semiconductor device fabrication method of claim 12, further comprising applying solder to a top surface of the Nickel-Iron layer.

14. The semiconductor device fabrication method of claim 11, further comprising:

forming the dielectric layer upon a substrate;

forming a metal line in the dielectric layer; and

forming a via between and contacting the metal line and the barrier layer.

15. The semiconductor device fabrication method of claim 11, wherein sidewalls of the barrier layer, the plating layer, the first Nickel layer, the Copper layer, the second Nickel layer, and the Nickel-Iron layer are all coplanar.