Method for manufacturing semiconductor device with oxide semiconductor ohmic conatct layers

• US 9,397,194 B2
• Filed: 07/02/2015
• Issued: 07/19/2016
• Est. Priority Date: 09/01/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo
• Primary Examiner(s): Dulka, John P
• Application Number:
  US14/790,609
• Publication Number:
  US 20150303280A1
• Time in Patent Office: 383 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/26 including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24 , e.g. alloys
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor structure in which a source electrode and a drain electrode formed from a metal material are in direct contact with an oxide semiconductor film may lead to high contact resistance. One cause of high contact resistance is that a Schottky junction is formed at a contact plane between the source and drain electrodes and the oxide semiconductor film. An oxygen-deficient oxide semiconductor layer which includes crystal grains with a size of 1 nm to 10 nm and has a higher carrier concentration than the oxide semiconductor film serving as a channel formation region is provided between the oxide semiconductor film and the source and drain electrodes.

Claims

1. A method for manufacturing a semiconductor device, comprising steps of:

forming a gate electrode over an insulating surface;

forming a gate insulating layer over the gate electrode by sputtering;

forming a first semiconductor layer over the gate insulating layer by sputtering without exposure to air after forming the gate insulating layer;

forming a second semiconductor layer over the first semiconductor layer by sputtering; and

patterning the second semiconductor layer to form a source region and a drain region over the first semiconductor layer,

wherein the first semiconductor layer is an oxide semiconductor layer, and

wherein the source region and the drain region are oxide semiconductor layers containing indium, gallium, and zinc, and have a lower oxygen concentration than the first semiconductor layer, and

wherein the source region and the drain region include a crystal grain with a size of 1 nm to 10 nm.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first semiconductor layer contains indium, gallium, and zinc.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the source region and the drain region are formed over the first semiconductor layer without exposure to air.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of subjecting a surface of the gate insulating layer to oxygen radical treatment before forming the first semiconductor layer.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a first metal layer over the source region and a second metal layer over the drain region.

6. The method for manufacturing a semiconductor device according to claim 5, wherein the first metal layer is a source electrode layer and the second metal layer is a drain electrode layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein an oxygen concentration in the gate insulating layer has a gradient, and the oxygen concentration in the gate insulating layer increases toward an interface between the gate insulating layer and the first semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the gate insulating layer has a peak of the oxygen concentration at the interface between the gate insulating layer and the oxide semiconductor layer.

9. A method for manufacturing a semiconductor device, comprising steps of:

forming a gate electrode over an insulating surface;

forming a gate insulating layer over the gate electrode by sputtering;

forming a first semiconductor layer over the gate insulating layer by sputtering without exposure to air after forming the gate insulating layer;

forming a second semiconductor layer over the first semiconductor layer by sputtering; and

patterning the second semiconductor layer to form a source region and a drain region over the first semiconductor layer;

wherein the first semiconductor layer is an oxide semiconductor layer, and

wherein the source region and the drain region are oxide layers containing indium, gallium, and zinc, and have a lower oxygen concentration than the first semiconductor layer, and

wherein the source region and the drain region include a crystal grain with a size of 1 nm to 10 nm.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the first semiconductor layer contains indium, gallium, and zinc.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the source region and the drain region are formed over the first semiconductor layer without exposure to air.

12. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of subjecting a surface of the gate insulating layer to oxygen radical treatment before forming the first semiconductor layer.

13. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of forming a first metal layer over the source region and a second metal layer over the drain region.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the first metal layer is a source electrode layer and the second metal layer is a drain electrode layer.

15. The method for manufacturing a semiconductor device according to claim 9, wherein an oxygen concentration in the gate insulating layer has a gradient, and the oxygen concentration in the gate insulating layer increases toward an interface between the gate insulating layer and the first semiconductor layer.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the gate insulating layer has a peak of the oxygen concentration at the interface between the gate insulating layer and the first semiconductor layer.