Methods of forming multi-Vt III-V TFET devices

• US 9,397,199 B1
• Filed: 01/11/2016
• Issued: 07/19/2016
• Est. Priority Date: 01/11/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kwon, Unoh, Krishnan, Siddarth A., Narayanan, Vijay, Sleight, Jeffrey
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US14/992,209
• Time in Patent Office: 190 Days
• Field of Search: 438/424, 257/343
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02351 treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
• CPC Class Codes: H01L 21/2686 using incoherent radiation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7391 Gated diode structures

Abstract

The disclosure generally relates to a method for forming multiple III-V Tunnel Field-Effect Transistors (III-V TFETs) microchips in which each TFET has a different threshold voltage (Vt) or work-function. In one embodiment of the disclosure, four TFETs are formed on a substrate. Each TFET has a source, drain and a gate electrode. Each gate electrode is then processed independently to provide a substantially different threshold voltage. Each TFET will have an intrinsic channel.

Claims

1. A method to form a device having multiple tunnel field-effect transistors (TFETs) with each TFET having a different work-function, the method comprising:

forming a first, second, third and fourth TFET device, each TFET device having a source electrode, a drain electrode and a gate electrode and each gate electrode having a dipole formation layer and a first gate oxide layer;

forming a first barrier metal layer over the first gate oxide layer for each of the first, second, third and fourth III-V TFET devices;

removing the first barrier metal layer from each of the first III-V TFET device and the second III-V TFET device;

removing the first gate oxide layer from the first III-V TFET device and the second III-V TFET device;

removing the first barrier metal layer from the third III-V TFET device and the fourth III-V TFET device;

depositing a second dielectric layer over each of the first, second, third and fourth III-V TFET devices, the second dielectric layer comprising HFO₂;

depositing a second barrier metal layer over each of the first, second, third and fourth III-V TFET devices;

removing the second barrier metal layers from each of the second III-V TFET device and third III-V TFET device;

depositing a third dielectric layer over each of the first, second, third and fourth III-V TFET devices, the third dielectric layer comprising La₂O₃;

annealing each of the first, second, third and fourth III-V TFET devices to diffuse the third dielectric layer into one or more adjacent layers;

removing the third dielectric layer from each of the first, second, third and fourth III-V TFET devices; and

depositing a final metal layer over each of the first, second, third and fourth III-V TFET devices layers to form four TFETs with each TFET having a different threshold voltage.