Trench gate FET with self-aligned source contact

• US 9,397,213 B2
• Filed: 08/29/2014
• Issued: 07/19/2016
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Qin, Ganming, de Frsart, Edouard, Ku, Pon Sung, Petras, Michael, Zitouni, Moaniss, Zupac, Dragan
• Primary Examiner(s): Abdelaziez, Yasser A
• Assistant Examiner(s): Lu, Farun
• Application Number:
  US14/473,327
• Publication Number:
  US 20160064556A1
• Time in Patent Office: 690 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.

Claims

1. A semiconductor device, comprising:

a substrate;

a semiconductor layer disposed at the substrate and having a first conductivity type;

first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode;

a body region disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench, the body region having a second conductivity type different than the first conductivity type;

a source contact region disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench, the source contact region having the first conductivity type; and

wherein;

the source contact region extends from the surface of the semiconductor layer to a first depth in the semiconductor layer; and

the body region extends from a second depth to a third depth in the semiconductor layer, the second depth greater than the first depth, such that the source contact region and the body region are separated by a region of the semiconductor layer.

2. The semiconductor device of claim 1, wherein:

the semiconductor layer has a first doping concentration; and

the source contact region has a second doping concentration greater than the first doping concentration.

3. The semiconductor device of claim 1, wherein:

the first and second trenches extend from the surface to a depth greater than the third depth.

4. The semiconductor device of claim 1, wherein:

the first and second trenches each further includes a corresponding portion of a shield electrode disposed below the gate electrode.

5. The semiconductor device of claim 1, wherein:

each of the first and second trenches further includes an insulating layer between a top of the gate electrode and a top of the trench.

6. The semiconductor device of claim 5, wherein:

the insulating layer has a thickness between 0.1 to 2.0 micrometers.

7. The semiconductor device of claim 1, wherein:

the semiconductor layer comprises an N-type semiconductor layer with a first doping concentration;

the source contact region comprises an N-type region with a second doping concentration greater than the first doping concentration; and

the body region comprises a high-voltage P-type (PHV) region.

8. A method for forming a semiconductor device, the method comprising:

forming a plurality of trenches in a semiconductor layer of the semiconductor device, each trench having a corresponding gate electrode;

forming a plurality of body regions below a surface of the semiconductor layer, each body region extending between adjacent sidewalls of a corresponding pair of adjacent trenches of the plurality of trenches and having a second conductivity type different than a first conductivity type of the semiconductor layer;

forming a plurality of source contact regions in the semiconductor layer, each source contact region disposed between a corresponding body region of the plurality of body regions and the surface of the semiconductor layer and extending between adjacent sidewalls of a corresponding pair of adjacent trenches, the source contact region having the first conductivity type; and

wherein;

forming the plurality of source contact regions comprises forming the plurality of source contact regions so that each source contact region extends from the surface of the semiconductor layer to a first depth in the semiconductor layer; and

forming the plurality of body regions comprises forming the plurality of body regions so that each body region extends from a second depth to a third depth in the semiconductor layer, the second depth greater than the first depth, so that each source contact region is separated from a corresponding body region by a region of the semiconductor layer.

9. The method of claim 8, wherein:

forming the plurality of body regions comprises performing a first blanket ion implant process.

10. The method of claim 9, wherein:

performing the first blanket ion implant process comprises performing the first blanket ion implant process at an implant energy between 700 and 900 kilo-electron-volts.

11. The method of claim 9, wherein:

forming the plurality of source contact regions comprises performing a second blanket ion implant process.

12. The method of claim 8, wherein:

forming the plurality of source contact regions comprises performing a blanket ion implant process to form the plurality of source contact regions with a doping concentration higher than a doping concentration of the semiconductor layer.

13. The method of claim 8, wherein forming the plurality of trenches comprises:

forming, in each trench, a corresponding portion of a shield electrode below the gate electrode.

14. The method of claim 8, wherein forming the plurality of trenches comprises:

forming, in each trench, an insulating layer between a top of the gate electrode and a top of the trench.

15. The method of claim 14, wherein:

forming the insulating layer comprises forming the insulating layer with a thickness between 0.1 to 2.0 micrometers.

16. A semiconductor device formed using the method of claim 8.