Semiconductor device

• US 9,397,224 B2
• Filed: 08/05/2014
• Issued: 07/19/2016
• Est. Priority Date: 10/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Bachner, Robert
• Assistant Examiner(s): REIDA, MOLLY KAY
• Application Number:
  US14/451,686
• Publication Number:
  US 20140339557A1
• Time in Patent Office: 714 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers. The buffer layers are provided between the semiconductor layer forming a channel formation region and the source and drain electrode layers in order to particularly relieve an electric field in the vicinity of a drain edge and improve the withstand voltage of the transistor.

Claims

1. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first buffer layer having n-type conductivity on and in contact with the oxide semiconductor layer;

a second buffer layer having n-type conductivity on and in contact with the oxide semiconductor layer;

a source electrode layer on the first buffer layer, wherein the first buffer layer extends beyond an inner side edge of the source electrode layer; and

a drain electrode layer on the second buffer layer, wherein the second buffer layer extends beyond an inner side edge of the drain electrode layer,

wherein inner side edges of the first buffer layer and the second buffer layer are tapered,

wherein the first buffer layer and the second buffer layer comprise an oxide of tin, and

wherein the oxide semiconductor layer includes crystals whose c-axes are aligned in a direction perpendicular to one surface of the oxide semiconductor layer and whose a-b planes are not aligned with each other.

2. The semiconductor device according to claim 1, wherein the first buffer layer and the second buffer layer further comprise an oxide of indium and an oxide of silicon.

3. The semiconductor device according to claim 1, further comprising an insulating layer over the source electrode layer and the drain electrode layer, wherein the insulating layer is in contact with a surface portion of the oxide semiconductor layer.

4. The semiconductor device according to claim 3, wherein the insulating layer is an oxygen supply layer.

5. The semiconductor device according to claim 1, wherein the first buffer layer and the second buffer layer have a stacked structure.

6. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first buffer layer having n-type conductivity on and in contact with the oxide semiconductor layer;

a second buffer layer having n-type conductivity on and in contact with the oxide semiconductor layer;

a source electrode layer on the first buffer layer, wherein the first buffer layer extends beyond an inner side edge of the source electrode layer; and

a drain electrode layer on the second buffer layer, wherein the second buffer layer extends beyond an inner side edge of the drain electrode layer,

wherein inner side edges of the first buffer layer and the second buffer layer are tapered,

wherein the first buffer layer and the second buffer layer comprise an oxide of tin,

wherein a surface portion of the oxide semiconductor layer between the first buffer layer and the second buffer layer is etched, and

wherein the oxide semiconductor layer includes crystals whose c-axes are aligned in a direction perpendicular to one surface of the oxide semiconductor layer and whose a-b planes are not aligned with each other.

7. The semiconductor device according to claim 6, wherein the first buffer layer and the second buffer layer further comprise an oxide of indium and an oxide of silicon.

8. The semiconductor device according to claim 6, further comprising an insulating layer over the source electrode layer and the drain electrode layer, wherein the insulating layer is in contact with the surface portion of the oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein the insulating layer is an oxygen supply layer.

10. The semiconductor device according to claim 6, wherein the first buffer layer and the second buffer layer have a stacked structure.