Logarithmic amplifier with universal demodulation capabilities

• US 9,397,382 B2
• Filed: 03/14/2014
• Issued: 07/19/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: DockOn AG
• Original Assignee: DockOn AG
• Inventors: Brown, Forrest, Rada, Patrick, Dupuy, Alexandre
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US14/214,437
• Publication Number:
  US 20140266420A1
• Time in Patent Office: 858 Days
• Field of Search: 329/347, 329/349, 329/352, 329/353, 329/369, 329/367, 327/350, 331/174, 455/336
• US Class Current: 1/1
• CPC Class Codes: H01P 5/19 of the junction type
• CPC Class Codes: H01Q 21/0075 Stripline fed arrays H01Q21/065 takes precedence
• CPC Class Codes: H01Q 7/00 Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• CPC Class Codes: H03D 1/08 by means of non-linear two-pole elements H03D1/22, H03D1/26, H03D1/28 take precedence
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H03D 11/04 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H03D 11/08 by means of semiconductor devices having more than two electrodes
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 2200/0098 by compensating temperature induced variations
• CPC Class Codes: H03D 7/02 by means of diodes H03D7/14 - H03D7/22 take precedence
• CPC Class Codes: H03D 7/12 by means of semiconductor devices having more than two electrodes H03D7/14 - H03D7/22 take precedence
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03D 7/166 using two or more quadrature frequency translation stages
• CPC Class Codes: H03F 1/08 Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03G 11/04 Limiting level dependent on strength of signal; Limiting level dependent on strength of carrier on which signal is modulated H03G11/008 takes precedence

Abstract

A logarithmic amplifier (LDA) is described that includes an amplifier configured to oscillate a modulated input signal, a feedback establishing a 180 degree phase shift between the amplifier input and the output and maintaining oscillation of the input signal, a parallel resonant circuit connected to the amplifier output causing the amplifier to resonate at or around a center frequency, and a controller connected to the amplifier input cyclically terminating oscillation of the input signal each time a pre-determined threshold of current is detected, the controller including a low pass filter configured to generate a second output signal having a repetition frequency. The LDA may be used for AM with or without a PLL and/or a superhetrodyne. The LDA may be implemented as a mixer and used for phase demodulation. The LDA may be used for phase demodulation. The LDA may be used in place of a low noise amplifier.

Claims

1. A logarithmic amplifier, comprising:

an amplifier circuit configured to receive an input signal at an amplifier input, oscillate the input signal, and generate a first output signal at an amplifier output, wherein the input signal includes a modulated signal to be detected and electrical noise;

a feedback circuit coupled to the amplifier output and the amplifier input and configured to establish a 180 degree phase shift between the input signal and the first output signal, the feedback circuit including a single capacitor configured to maintain oscillation of the input signal;

a parallel resonant circuit directly connected to the amplifier output and configured to cause the amplifier circuit to resonate at or around a center frequency; and

a controller circuit directly connected to the amplifier input and configured to cyclically terminate oscillation of the input signal each time a pre-determined threshold of voltage is detected, the controller circuit including a low pass filter configured to generate a second output signal having a repetition frequency.

2. The logarithmic amplifier of claim 1, wherein the modulated signal is amplitude modulated or phase modulated, wherein the first output signal has an approximate bell shape in the frequency domain, and wherein the modulated signal is demodulated when a frequency of the input signal is adjusted to a center of the bell shape.

3. The logarithmic amplifier of claim 1, wherein the controller circuit includes an RC circuit and the low pass filter is a combination of a RC circuit and a diode coupled between the amplifier input and the RC circuit.

4. The logarithmic amplifier of claim 1, wherein the controller circuit includes an RC circuit and the low pass filter is a combination of a RC circuit and an inductor coupled between the amplifier input and the RC circuit.

5. The logarithmic amplifier of claim 1, further comprising a bias coupled to the amplifier input.

6. The logarithmic amplifier of claim 5, wherein the bias is configured to temperature compensate the amplifier circuit.

7. The logarithmic amplifier of claim 5, wherein the bias is a temperature compensated constant current feed.

8. The logarithmic amplifier of claim 1, further comprising a low pass filter coupled to the amplifier output and configured to generate a third output signal that is a substantially regenerated time sampled copy of the envelope of the input signal including any modulation after any RF frequency component has been removed.

9. The logarithmic amplifier of claim 8, further comprising a temperature controlled bias coupled to the amplifier input.

10. The logarithmic amplifier of claim 8, further comprising a matching circuit coupled between the amplifier output and the low pass filter.

11. The logarithmic amplifier of claim 8, further comprising an anti-aliasing filter and an analog-to-digital converter coupled to an output of the low pass filter.

12. The logarithmic amplifier of claim 8, further comprising a frequency to voltage converter, an anti-aliasing filter, and an analog-to-digital converter coupled to an output of the low pass filter.

13. The logarithmic amplifier of claim 8, further comprising a digital shaper, a frequency meter, and a scaling circuit coupled to an output of the low pass filter.

14. The logarithmic amplifier of claim 1, further comprising one or more matching circuits coupled to the input of the amplifier input.

15. The logarithmic amplifier of claim 14, further comprising an isolator coupled to the amplifier input or coupled between the one or more matching circuits.

16. The logarithmic amplifier of claim 15, further comprising a matching network and a low pass filter coupled to the amplifier output and configured to generate a third output signal.

17. The logarithmic amplifier of claim 15, further comprising a matching network and a low pass filter coupled to the amplifier input and configured to generate a third output signal.

18. The logarithmic amplifier of claim 15, further comprising a matching network and a low pass filter coupled to the parallel resonant circuit and configured to generate a third output signal.

19. The logarithmic amplifier of claim 15, further comprising a matching network coupled to the low pass filter and configured to generate the second output signal.

20. The logarithmic amplifier of claim 1, further comprising:

a super-heterodyne stage coupled to the amplifier input, configured to translate the input signal to an intermediate frequency; and

a phase locked loop (PLL) coupled to the amplifier circuit, configured to voltage feed the oscillations of the input signal, and configured to output phase information of the input signal at a PLL output.

21. The logarithmic amplifier of claim 20, further comprising:

an analogue to digital converter (ADC) coupled to the PLL output, configured to convert the phase information to quadrature information.

22. The logarithmic amplifier of claim 20, further comprising:

one or more matching circuits coupled in between the super-heterodyne stage and the amplifier input; and

an isolator coupled to the amplifier input or coupled between the one or more matching circuits.

23. The logarithmic amplifier of claim 1, further comprising:

a phase locked loop (PLL) coupled to the amplifier circuit, configured to voltage feed the oscillations of the input signal, and configured to output phase information of the input signal at a PLL output.

24. The logarithmic amplifier of claim 20, further comprising:

an analogue to digital converter (ADC) coupled to the PLL output, configured to convert the phase information to quadrature information.

25. The logarithmic amplifier of claim 1, further comprising:

a phase locked loop (PLL) coupled to the amplifier output, configured to output module and phase information of the input signal at a PLL output.

26. The logarithmic amplifier of claim 25, wherein the PLL is configured to voltage feed the oscillations of the input signal, and wherein the PLL further comprises a switch that is fed by the second output signal of the amplifier circuit.

27. The logarithmic amplifier of claim 25, wherein the PLL further comprises:

a feedback loop coupled with the amplifier output; and

a phase/frequency comparator, wherein the PLL output is coupled to the phase/frequency comparator.

28. An amplitude demodulator, comprising:

a logarithmic amplifier detector (LDA) circuit, including;

an amplifier circuit configured to receive an input signal at an amplifier input, oscillate the input signal, and generate a first output signal at an amplifier output, wherein the input signal includes a modulated signal to be detected and electrical noise;

one or more matching circuits coupled to the input of the amplifier input;

an isolator coupled to the amplifier input or coupled between the one or more matching circuits;

a feedback circuit coupled to the amplifier output and the amplifier input and configured to establish a 180 degree phase shift between the input signal and the first output signal, the feedback circuit including a single capacitor configured to maintain oscillation of the input signal;

a parallel resonant circuit connected to the amplifier output and configured to cause the amplifier circuit to resonate at or around a center frequency; and

a controller circuit connected to the amplifier input and configured to cyclically terminate oscillation of the input signal each time a pre-determined threshold of voltage is detected, the controller circuit including a low pass filter configured to generate a second output signal having a repetition frequency; and

a phase lock loop (PLL) circuit coupled to the LDA circuit and configured to lock the center frequency of the LDA circuit to a reference frequency.

29. The amplitude demodulator of claim 28, wherein the LDA circuit further includes a temperature compensated bias coupled to the amplifier input.

30. The amplitude demodulator of claim 29, wherein the PLL circuit includes a sampler coupled to a controller of a switch, a comparator coupled to a first side of the switch, and a low pass filter to a second side of the switch, wherein the first output signal or the second output signal is coupled to the sampler, wherein the switch is open when the comparator is disconnected and a quenching pulse is not present and the switch is closed when the comparator is connected and the quenching pulse is present, wherein the switch enables the low pass filter to couple the PLL to an input of the temperature compensated bias, and wherein the comparator is fed by the amplifier output divided by N and is fed from the reference frequency divided by M.