Semiconductor device and display device

• US 9,397,649 B2
• Filed: 09/09/2013
• Issued: 07/19/2016
• Est. Priority Date: 09/11/2012
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Shimada, Yukimine, Nishiki, Hirohiko, Kitoh, Kenichi
• Primary Examiner(s): Nguyen, Tung X
• Assistant Examiner(s): LE, THANG XUAN
• Application Number:
  US14/426,818
• Publication Number:
  US 20150236687A1
• Time in Patent Office: 1,044 Days
• Field of Search: 324/762.01, 324/762.02, 324/762.05, 324/750.01, 324/750.02, 324/756.05, 324/73.1, 324/601
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2320/048 using evaluation of the usage time
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

A semiconductor device is provided with an oxide semiconductor thin-film transistor (TFT); a calibration electrode that is positioned so as to face an oxide semiconductor layer with an insulating layer therebetween, and, when viewed from the direction of the substrate normal line, overlaps at least part of a gate electrode with the oxide semiconductor layer interposed therebetween; and a calibration voltage setting circuit that determines the voltage to be applied to the calibration electrode. The calibration voltage setting circuit is provided with: a monitor TFT that is configured using a second oxide semiconductor layer, which is substantially the same as the oxide semiconductor layer of the oxide semiconductor TFT; a detection circuit that is configured so as to be able to measure the device characteristics of the monitor TFT; and a voltage determination circuit that determines the voltage to be applied to the calibration electrode on the basis of the measured device characteristics.

Claims

1. A semiconductor device, comprising:

a substrate;

an oxide semiconductor thin film transistor formed on said substrate and having a gate electrode, an oxide semiconductor layer facing said gate electrode with a first insulating layer therebetween, and a source electrode and a drain electrode connected to said oxide semiconductor layer;

a calibration electrode facing said oxide semiconductor layer with a second insulating layer therebetween and overlapping, when viewed from a direction normal to the substrate, at least part of said gate electrode, said oxide semiconductor layer being interposed between said gate electrode and said calibration electrode; and

a calibration voltage setting circuit that determines a voltage to be applied to said calibration electrode;

wherein said calibration voltage setting circuit comprises;

a monitor thin film transistor formed on the substrate and comprising a second oxide semiconductor layer being made of the same oxide semiconductor material as the oxide semiconductor layer of said oxide semiconductor thin film transistor, said monitor thin film transistor having a gate electrode, a source electrode, and a drain electrode;

a detection circuit that is configured to measure device characteristics of said monitor thin film transistor; and

a voltage determination circuit that determines said voltage to be applied to the calibration electrode in accordance with said device characteristics that are measured by the detection circuit.

2. The semiconductor device according to claim 1, further comprising:

a second calibration electrode facing said gate electrode of the monitor thin film transistor with said second oxide semiconductor layer thereof interposed therebetween when viewed from the direction normal to the substrate,

wherein, when said device characteristics measured by the detection circuit are within a prescribed range, said voltage determination circuit determines that a voltage applied to said second calibration electrode during said measurement is the voltage to be applied to the calibration electrode, and

wherein, when said measured device characteristics are not within the prescribed range, said voltage determination circuit causes the voltage applied to said second calibration electrode to change, and the detection circuit repeats detection of the device characteristics of the monitor thin film transistor while the voltage that has been caused to change is applied to the second calibration electrode.

3. The semiconductor device according to claim 1, wherein said calibration voltage setting circuit sets the voltage to be applied to said calibration electrode when a start signal is received.

4. The semiconductor device according to claim 3, wherein said start signal is regularly sent to said calibration voltage setting circuit in predetermined time intervals.

5. The semiconductor device according to claim 3, wherein said start signal is sent to said calibration voltage setting circuit in response to user input.

6. The semiconductor device according to claim 1,

wherein a reference gate voltage is applied to the gate electrode of the monitor thin film transistor,

wherein a reference source voltage is applied to the source electrode of the monitor thin film transistor, and

wherein the detection circuit detects a value of a current flowing through the drain electrode of the monitor thin film transistor.

7. The semiconductor device according to claim 1, wherein an active layer of said oxide semiconductor thin film transistor includes indium-gallium-zinc-oxide.

8. The semiconductor device according to claim 7, wherein said indium-gallium-zinc-oxide is crystalline indium-gallium-zinc-oxide.

9. The semiconductor device according to claim 1, wherein the gate electrode of the oxide semiconductor thin film transistor and the gate electrode of the monitor thin film transistor are connected to the same gate bus line.

10. A display device, comprising:

the semiconductor device according to claim 1,

wherein said display device includes a display area and a non-display area that is disposed outside of the display area,

wherein the oxide semiconductor thin film transistor of said semiconductor device is provided within said display area, and

wherein said monitor thin film transistor of said semiconductor device is provided within said non-display area.

11. The display device according to claim 10,

wherein said non-display area is provided with a driver circuit comprising an element that includes said oxide semiconductor and a third calibration electrode provided on said element, and

wherein said calibration voltage setting circuit is configured so as to determine a voltage applied to said third calibration electrode of said driver circuit.