×

Low power externally biased power-on-reset circuit

  • US 9,397,654 B2
  • Filed: 10/09/2014
  • Issued: 07/19/2016
  • Est. Priority Date: 10/09/2014
  • Status: Active Grant
First Claim
Patent Images

1. A power-on-reset circuit for generating a power-on-reset signal upon detecting that a supply voltage has reached a desired level comprising:

  • a sense circuit comprising;

    (i) an inverter powered by a known bias voltage;

    (ii) a feedback circuit powered by the supply voltage; and

    (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level; and

    a delayed buffer coupled to the output node of the sense circuit that generates the power-on-reset signal in response to the voltage transition;

    wherein the feedback circuit shuts off the sense circuit in response to the voltage transition;

    wherein the power-on-reset circuit generates the power-on-reset signal for a local system; and

    wherein the known bias voltage is provided by an external system;

    the sense circuit further comprising;

    a voltage divider coupled to the supply voltage and providing a divided voltage to an inverter input node;

    wherein the inverter comprises an inverter output node and the inverter input node; and

    wherein the inverter output node is the output node of the sense circuit;

    the voltage divider comprising;

    a first transistor that is gate coupled to the inverter input node, and that provides a first source-drain path between the supply voltage and the inverter input node; and

    a second transistor that is gate coupled to the inverter input node, and that provides a second source-drain path along a circuit branch between the input of the inverter and a ground node.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×