System and method for lifetime specific LDPC decoding

• US 9,397,701 B1
• Filed: 03/11/2013
• Issued: 07/19/2016
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Inventors: Micheloni, Rino, Onufryk, Peter Z., Marelli, Alessia, Norrie, Christopher I. W.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Vallecillo, Kyle
• Application Number:
  US13/792,831
• Time in Patent Office: 1,226 Days
• Field of Search: 714/763, 714/780, 714/E11.034, 365/185.2, 365/185.18, 365/185.24
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/3723 using means or methods for the initialisation of the decoder
• CPC Class Codes: H03M 13/612 Aspects specific to channel or signal-to-noise ratio estimation H03M13/63 takes precedence

Abstract

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of the memory storage module, wherein each of the plurality of lifetime specific LLR look-up tables comprises a plurality of LLRs representative of a specific point in the lifetime of the memory storage module for each of the plurality of soft-decision bits. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

Claims

1. A method of providing log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder, the method comprising:

storing a plurality of lifetime specific LLR look-up tables for a nonvolatile memory storage module, each of the lifetime specific LLR tables including LLRs representative of a threshold voltage distribution of flash chips of the nonvolatile memory storage module at a point in the lifetime of the nonvolatile memory storage module;

reading an LDPC encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword;

identifying a current point in the lifetime of the nonvolatile memory storage module based on the current bit error rate (BER) of one or more of the flash chips of the nonvolatile memory storage module;

selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables based upon the identified current point in the lifetime of the nonvolatile memory storage module;

extracting the LLRs from the current lifetime specific LLR look-up table for each of the soft-decision bits; and

providing the extracted LLRs to an LDPC decoder for decoding of the codeword.

2. The method of claim 1, wherein the nonvolatile memory storage module is a NAND-based flash memory module.

3. The method of claim 1, wherein the nonvolatile memory storage module is selected from the group consisting of a single-level cell (SLC) memory storage module, a multi-level cell (MLC) memory storage module and a triple-level (TLC) memory storage module.

4. The method of claim 1, further comprising generating the plurality of lifetime specific LLR look-up tables, each of the lifetime specific LLR tables including the LLRs representative of a threshold voltage distribution of one or more of the plurality of individual flash chips at a point in the lifetime of the one or more of the plurality of individual flash chips.

5. The method of claim 1, wherein the nonvolatile memory storage module comprises a plurality of specific regions comprising one or more individual flash chips and wherein one or more of the plurality of lifetime specific LLR look-up tables comprises LLRs representative of a threshold voltage distribution at a point in the lifetime of one more of the plurality of specific regions.

6. The method of claim 1, wherein the plurality of soft-decision reference voltages are determined by non-uniform partitioning of a threshold voltage distribution associated with the nonvolatile memory storage module.

7. The method of claim 1, wherein reading the LDPC encoded codeword further comprises:

identifying at least one hard-decision reference voltage in a threshold voltage distribution associated with the nonvolatile memory storage module;

identifying an overlap region around each of the at least one hard-decision reference voltages;

partitioning the overlap region into a plurality of threshold voltage ranges, each threshold voltage range bounded by two soft-decision reference voltages to establish non-uniform partitioning of the threshold voltage distribution;

applying the soft-decision reference voltages to a cell of the nonvolatile memory storage module; and

sensing a voltage level of the cell.

8. The method of claim 1, wherein the lifetime specific LLR look-up table is asymmetric.

9. The method of claim 1, wherein the plurality of soft-decision reference voltages is equal to one and the plurality of soft-decision bits representative of the codeword is equal to two.

10. A nonvolatile memory controller for providing log likelihood ratios (LLRs) for low-density parity check (LDPC) decoding, the controller comprising:

circuitry for storing a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of a nonvolatile memory storage module, each of the plurality of lifetime specific LLR look-up tables including LLRs representative of threshold voltage distributions of flash chips of the nonvolatile memory storage module at a point in the lifetime of the nonvolatile memory storage module;

read circuitry for reading an LDPC encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages and for identifying a plurality of soft-decision bits representative of the codeword;

circuitry for identifying a current point in the lifetime of the nonvolatile memory storage module based on the current bit error rate (BER) of one or more of the flash chips of the nonvolatile memory storage module; and

circuitry for selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables for the nonvolatile memory storage module based upon the identified current point in the lifetime of the nonvolatile memory storage module.

11. The controller of claim 10, wherein the nonvolatile memory storage module is a NAND-based flash memory module.

12. The controller of claim 10, wherein the nonvolatile memory storage module is selected from the group consisting of a single-level cell (SLC) memory storage module, a multi-level cell (MLC) memory storage module and a triple-level cell (TLC) memory storage module.

13. The controller of claim 10, wherein at least one of the plurality of lifetime specific LLR look-up tables represents each decade of bit error rate (BER) of the lifetime of the nonvolatile memory storage module.

14. The controller of claim 10, wherein the nonvolatile memory storage module comprises a plurality of specific regions comprising one or more individual flash chips and wherein one or more of the plurality of lifetime specific LLR look-up tables comprises LLRs representative of a threshold voltage distribution at a point in the lifetime of one or more of the plurality of specific regions.

15. The controller of claim 10, wherein the plurality of soft-decision reference voltages are determined by non-uniform partitioning of a threshold voltage distribution associated with the nonvolatile memory storage module.

16. The controller of claim 10, wherein the read circuitry further comprises circuitry for identifying at least one hard-decision reference voltage in a threshold voltage distribution associated with the nonvolatile memory storage module, identifying an overlap region around each of the at least one hard-decision reference voltages, partitioning the overlap region into a plurality of threshold voltage ranges, each threshold voltage range bounded by two soft-decision reference voltages to establish non-uniform partitioning of the threshold voltage distribution, applying the soft-decision reference voltages to a cell of the nonvolatile memory storage module and sensing a voltage level of the cell.

17. The controller of claim 10, further comprising, circuitry to extract the LLRs from the current lifetime specific LLR look-up table for each of the soft-decision bits and to provide the extracted LLRs to an LDPC decoder for decoding of the codeword.

18. The controller of claim 10, wherein at least one of the plurality of lifetime specific LLR look-up tables is asymmetric.

19. A nonvolatile memory controller for providing log likelihood ratios (LLRs) for low-density parity check (LDPC) decoding, the controller comprising:

circuitry for storing a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of a nonvolatile memory storage module, each of the plurality of lifetime specific LLR look-up tables including LLRs representative of threshold voltage distributions of flash chips of the nonvolatile memory storage module at a point in the lifetime of the nonvolatile memory storage module, at least one of the plurality of lifetime specific LLR look-up tables representing each decade of bit error rate (BER) of the lifetime of the nonvolatile memory storage module;

read circuitry for reading an LDPC encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages and for identifying a plurality of soft-decision bits representative of the codeword;

circuitry for identifying a current point in the lifetime of the nonvolatile memory storage module based on the current bit error rate (BER) of one or more of the flash chips of the nonvolatile memory storage module;

circuitry for selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables for the nonvolatile memory storage module based upon the identified current point in the lifetime of the nonvolatile memory storage module; and

circuitry to extract the LLRs from the current lifetime specific LLR look-up table for each of the soft-decision bits and to provide the extracted LLRs to an LDPC decoder for decoding of the codeword.

20. The controller of claim 19, wherein at least one of the plurality of lifetime specific LLR look-up tables is asymmetric.

22. The controller of claim 19, wherein at least one of the plurality of lifetime specific LLR look-up tables is asymmetric.

21. A nonvolatile memory system comprising:

a nonvolatile memory storage module;

read circuitry coupled to the nonvolatile memory storage module for reading a low-density parity check (LDPC) encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages and for identifying a plurality of soft-decision bits representative of the codeword;

a plurality of lifetime specific log likelihood ratio (LLR) look-up tables representative of the lifetime threshold voltage distribution of the nonvolatile memory storage module, the plurality of lifetime specific LLR look-up tables stored in the nonvolatile memory system, each of the plurality of lifetime specific LLR look-up tables including a plurality of LLRs representative of a specific point in the lifetime of the nonvolatile memory storage module;

circuitry coupled to the nonvolatile memory storage module for identifying a current point in the lifetime of the nonvolatile memory storage module based on the current BER of the nonvolatile memory storage module;

circuitry for selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables for the nonvolatile memory storage module based upon the identified current point in the lifetime of the nonvolatile memory storage module; and

circuitry coupled to the nonvolatile memory storage module to extract the LLRs from the lifetime specific LLR look-up table for each of the soft-decision bits and to provide the extracted LLRs to an LDPC decoder for decoding of the codeword.