Split-path equalizer and related methods, devices and systems

• US 9,397,868 B1
• Filed: 10/09/2013
• Issued: 07/19/2016
• Est. Priority Date: 12/11/2012
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Hossain, Masum, Zerbe, Jared L.
• Primary Examiner(s): Washburn, Daniel
• Assistant Examiner(s): Singh, Amneet
• Application Number:
  US14/050,223
• Time in Patent Office: 1,014 Days
• Field of Search: 375/233, 375/232, 375/350, 375/229, 708/328, 714/704
• US Class Current: 1/1
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Claims

1. An integrated circuit, comprising:

an electrical contact adapted to receive an incoming data signal from a path external to the integrated circuit;

circuitry operatively coupled to the electrical contact so as to receive the incoming data signal and equalize the incoming data signal using a first linear equalizer to generate a first output;

circuitry operatively coupled to the electrical contact so as to receive the incoming data signal and equalize the incoming data signal using a second linear equalizer to generate a second output in parallel with the first output; and

circuitry operatively coupled to the first output and to the second output to generate a clock therefrom;

wherein the second output is equalized differently than the first output according to equalization characteristics respective to the first linear equalizer and the second linear equalizer; and

wherein the circuitry to generate the clock comprises

a data sampler to receive the first output and to produce data samples therefrom,

an edge sampler to receive the second output and to produce edge samples therefrom, and

logic to receive the data samples and edge samples and to alternatively advance and delay a generated clock in dependence on the data samples and edge samples, to thereby generate the clock as a recovered clock from the incoming data signal.

2. The integrated circuit of claim 1, wherein the incoming data signal comprises a stream of digital symbols encoded to ensure a minimum transition density, and wherein the circuitry to generate further comprises a data sampler to sample the first output to produce at least one bit representing each digital symbol.

3. The integrated circuit of claim 2, wherein the incoming data signal is a differential signal encoded in a manner compliant with at least one standard selected from the group of a PCI Express standard, a Serial ATA standard, and a Display Port standard, and wherein:

the electrical contact is a first electrical contact; and

the integrated circuit further comprises

a second electrical contact, the first and second electrical contacts adapted to receive respective components of the differential signal,

a deserializer to receive the at least one bit and generate therefrom a sequence of parallel words, and

a decoder to convert the incoming data signal from the encoded manner compliant with the at least one encoding standard into decoded data.

4. The integrated circuit of claim 1, further comprising a register adapted to store an offset for data sampling relative to a reference clock, the offset dependent on a phase difference between the first output and the second output.

5. The integrated circuit of claim 1, wherein each of the first output and the second output are characterized by at least one equalization parameter shared by the other of the first output and the second output.

6. The integrated circuit of claim 1, wherein:

the integrated circuit further comprises a third equalizer circuit operatively coupled to the electrical contact, so as to receive the incoming data signal and generate an equalized incoming data signal;

the first and second equalizer circuits are operatively coupled to the third equalizer circuit, so as to each receive the equalized incoming data signal; and

each of the first and second equalizer circuits are each to further-equalize the equalized incoming data signal in parallel.

7. The integrated circuit of claim 6, wherein the third equalizer circuit comprises at least two distributed circuit elements to sequentially provide electrostatic discharge protection to the integrated circuit from the incoming data signal.

8. The integrated circuit of claim 1, wherein settings of each of the first linear equalizer and the second linear equalizer are configurable.

9. The integrated circuit of claim 1, wherein:

the circuitry to receive the incoming data signal from the electrical contact and to equalize the incoming data signal to generate the first equalized output is to use first equalization settings that boost signal margin of the incoming data signal; and

the circuitry to receive the incoming data signal from the electrical contact and to equalize the incoming data signal to generate the second equalized output is to use second equalization settings that equalize edge distribution of a single-bit response associated with the incoming data signal.

10. A clock recovery circuit, comprising:

an input adapted to receive an incoming data signal;

circuitry to receive the incoming data signal from the input and to equalize the incoming data signal using a first linear equalizer to generate a first equalized output;

a data sampler to receive the first equalized output and to generate data samples therefrom; and

circuitry to receive the incoming data signal from the input and to equalize the incoming data signal using a second linear equalizer to generate a second equalized output in parallel with the first output; and

an edge sampler to receive the second equalized output and to generate edge samples therefrom;

wherein the clock recovery circuit is to generate a recovered clock from the data samples and the edge samples, and wherein the first equalized output and the second equalized output are respectively equalized according to respective equalization characteristics of the first linear equalizer and the second linear equalizer.

11. The clock recovery circuit of claim 10, wherein the incoming data signal is a differential signal encoded in a manner compliant with at least one standard selected from the group of a PCI Express standard, a Serial ATA standard, and a Display Port standard, and wherein:

the input comprises at least two electrical contacts adapted to receive respective components of the differential signal;

the clock recovery circuit further comprises a deserializer to receive the at least one bit in the form of at least one serial stream of data and to generate therefrom a sequence of parallel words; and

the clock recovery circuit further comprises a decoder to convert the incoming data signal from the encoded manner compliant with the at least one standard into decoded data.

12. The clock recovery circuit of claim 10, wherein:

the circuitry to receive the incoming data signal from the input and to equalize the incoming data signal to generate the first equalized output is to use first equalization settings that boost signal margin of the incoming data signal; and

the circuitry to receive the incoming data signal from the input and to equalize the incoming data signal to generate the second equalized output is to use second equalization settings that equalize edge distribution of a single-bit response associated with the incoming data signal.

13. The clock recovery circuit of claim 12, wherein the first equalization settings are further adapted to maximize signal-to-noise ratio of the incoming data signal.

14. The clock recovery circuit of claim 12, further comprising:

circuitry to store a test pattern;

circuitry to compare the test pattern with a calibration sequence carried by the incoming data signal, and to generate comparison results; and

storage circuitry to store the first equalization settings and the second equalization settings;

wherein each of the first equalization settings and the second equalization settings stored in the storage circuitry are dependent on the comparison results.

15. The clock recovery circuit of claim 10, embodied in an integrated circuit having an electrical contact that is one of a signal pin of the integrated circuit and a contact pad of the integrated circuit, wherein:

the clock recovery circuit further comprises a third equalizer circuit operatively coupled to the input, so as to receive the incoming data signal and generate an equalized incoming data signal;

the first and second equalizer circuits are each operatively coupled to the third equalizer circuit, so as to each receive the equalized incoming data signal; and

each of the first and second equalizer circuits are to further equalize the equalized incoming data signal.

16. The clock recovery circuit of claim 15, wherein the third equalizer circuit comprises at least two distributed circuit elements to sequentially provide electrostatic discharge protection to the integrated circuit from the incoming data signal.

17. The clock recovery circuit of claim 10, wherein settings of each of the first linear equalizer and the second linear equalizer are configurable.

18. An integrated circuit adapted to receive incoming data signals from respective parallel conductive signaling lanes external to the integrated circuit, comprising:

at least one electrical contact for each signaling lane adapted to receive a respective one of the incoming data signals; and

a receiver for each respective incoming data signal adapted to receive the respective incoming data signal from the respective at least one electrical contact and to generate samples thereof, each receiver further comprising

circuitry to receive the respective incoming data signal and to equalize the respective incoming data signal using a first linear equalizer to generate a first output of the respective incoming data signal,

circuitry to receive the respective incoming data signal and to equalize the respective incoming data signal in parallel with the first output using a second linear equalizer to generate a second output, and

circuitry operatively coupled to the first output and to the second output for the respective incoming data signal to generate a clock therefrom;

wherein for each receiver the second output of the first incoming data signal is adapted to be equalized differently than the first output of the first incoming data signal according to respective equalization characteristics of the first linear equalizer and the second linear equalizer; and

wherein the circuitry to generate the clock for each receiver comprises

a data sampler to receive the first output and to produce data samples therefrom,

an edge sampler to receive the second output and to produce edge samples therefrom, and

logic to receive the data samples and edge samples and to alternatively advance and delay a generated clock in dependence on the data samples and edge samples, to thereby generate the clock as a recovered clock from the incoming data signal.

19. The integrated circuit of claim 18, wherein for each receiver:

the first linear equalizer is to use first equalization settings that boost signal margin of the respective incoming data signal; and

the second linear equalizer is to use second equalization settings that equalize edge distribution of a single-bit response associated with the respective incoming data signal.

20. The integrated circuit of claim 18, wherein for each receiver settings of each of the first linear equalizer and the second linear equalizer are configurable.

21. The integrated circuit of claim 18, wherein the integrated circuit further comprises for each receiver at least two distributed circuit elements to sequentially provide electrostatic discharge protection to the integrated circuit from the respective incoming data signal.