Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained

• US 9,400,617 B2
• Filed: 03/17/2014
• Issued: 07/26/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Fuentes, Marizonne Operio, Noble, Gianico Geonzon, Ponce, Cyrill
• Primary Examiner(s): Peyton, Tammara
• Application Number:
  US14/217,467
• Publication Number:
  US 20150006766A1
• Time in Patent Office: 862 Days
• Field of Search: 710/22, 710/308
• US Class Current: 1/1
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core'"'"'s descriptors¹ are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. ¹ Descriptors are set of instructions that is used to activate the DMA controller.

By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.

Claims

1. An apparatus, comprising:

a memory DMA (direct memory access) engine;

an IOC (input/output to cache) DMA engine;

a cache;

a dependency table configured to permit one of the memory DMA engine and IOC DMA engine to transmit data to the cache and to permit, in parallel, another one of the memory DMA engine and IOC DMA engine to drain data from the cache without processor intervention whenever a data buffer in the cache is filled or drained;

wherein the dependency table comprises a plurality of index fields, wherein each of the plurality of index fields comprises a plurality of buffer fields;

wherein the plurality of buffer fields comprises a first buffer field comprising a first plurality of sub-indices assigned to the memory DMA engine;

wherein the plurality of buffer fields comprises a second buffer field comprising a second plurality of sub-indices assigned to the IOC DMA engine;

wherein the cache comprises a first descriptor for the memory DMA engine and a second descriptor for the IOC DMA engine and wherein the first descriptor and the second descriptor point to a first data buffer in the cache.

2. The apparatus of claim 1, wherein the memory DMA engine can start transferring data between a memory and a first buffer in the cache with one of the plurality of buffer fields having a first value;

wherein the IOC DMA engine can start transferring data between the first buffer in the cache and an IO bus interface with the one of the plurality of buffer fields having a second value.

3. The apparatus of claim 2, wherein one of the memory DMA engine and IOC DMA engine updates the one of the plurality of buffer fields between being free and being allocated;

and wherein another one of the memory DMA engine and the IOC DMA engine monitors the one of the plurality of buffer fields as being free or as being allocated.

4. The apparatus of claim 3, wherein the memory DMA engine updates the one of the plurality of buffer fields for a read command and wherein the IOC DMA engine updates the one of the plurality of buffer fields for a write command.

5. The apparatus of claim 4, wherein the one of the plurality of buffer fields is free in response to data being transferred to a data buffer in the cache and the data being available to be drained from the data buffer.

6. The apparatus of claim 5, wherein the memory DMA engine can start transferring data between the memory and a second buffer in the cache with a second one of the plurality of buffer fields having the first value;

wherein the IOC DMA engine can start transferring data between the second buffer in the cache and the IO bus interface with the second one of the plurality of buffer fields having the second value.

7. The apparatus of claim 1, further comprising:

an intermediate processing DMA engine configured to process data from the cache.

8. The apparatus of claim 7, wherein the intermediate processing DMA engine can start transferring data between the cache and the intermediate processing DMA engine with one of the plurality of buffer fields having a second value.

9. A method, comprising:

permitting one of a memory DMA (Direct Memory Access) engine and IOC (input/output to cache) DMA engine to transmit data to a cache and permitting, in parallel, another one of the memory DMA engine and IOC DMA engine to drain data from the cache without processor intervention whenever a data buffer in the cache is filled or drained;

using a dependency table comprising a plurality of index fields, wherein each of the plurality of index fields comprises a plurality of buffer fields;

wherein the plurality of buffer fields comprises a first buffer field comprising a first plurality of sub-indices assigned to the memory DMA engine;

wherein the plurality of buffer fields comprises a second buffer field comprising a second plurality of sub-indices assigned to the IOC DMA engine;

wherein the cache comprises a first descriptor for the memory DMA engine and a second descriptor for the IOC DMA engine and wherein the first descriptor and the second descriptor point to a first data buffer in the cache.

10. The method of claim 9, wherein the memory DMA engine can start transferring data between a memory and a first buffer in the cache with one of the plurality of buffer fields having a first value;

wherein the IOC DMA engine can start transferring data between the first buffer in the cache and an IO bus interface with the one of the plurality of buffer fields having a second value.

11. The method of claim 10, wherein one of the memory DMA engine and IOC DMA engine updates the one of the plurality of buffer fields between being free and being allocated;

and wherein another one of the memory DMA engine and the IOC DMA engine monitors the one of the plurality of buffer fields as being free or as being allocated.

12. The method of claim 11, wherein the memory DMA engine updates the one of the plurality of buffer fields for a read command and wherein the IOC DMA engine updates the one of the plurality of buffer fields for a write command.

13. The method of claim 12, wherein the one of the plurality of buffer fields is free in response to data being transferred to a data buffer in the cache and the data being available to be drained from the data buffer.

14. The method of claim 13, wherein the memory DMA engine can start transferring data between the memory and a second buffer in the cache with a second one of the plurality of buffer fields having the first value;

wherein the IOC DMA engine can start transferring data between the second buffer in the cache and the IO bus interface with the second one of the plurality of buffer fields having the second value.

15. The method of claim 9, further comprising:

processing data, by an intermediate processing DMA engine, from the cache.

16. The method of claim 15, wherein the intermediate processing DMA engine can start transferring data between the cache and the intermediate processing DMA engine with one of the plurality of buffer fields having a second value.

17. An article of manufacture, comprising:

a non-transient computer-readable medium having stored thereon instructions that permit a method comprising;

permitting one of a memory DMA (Direct Memory Access) engine and IOC (input/output to cache) DMA engine to transmit data to a cache and permitting, in parallel, another one of the memory DMA engine and IOC DMA engine to drain data from the cache without processor intervention whenever a data buffer in the cache is filled or drained;

wherein the method further comprises;

using a dependency table comprising a plurality of index fields, wherein each of the plurality of index fields comprises a plurality of buffer fields;

wherein the plurality of buffer fields comprises a first buffer field comprising a first plurality of sub-indices assigned to the memory DMA engine;

wherein the plurality of buffer fields comprises a second buffer field comprising a second plurality of sub-indices assigned to the IOC DMA engine;

wherein the cache comprises a first descriptor for the memory DMA engine and a second descriptor for the IOC DMA engine and wherein the first descriptor and the second descriptor point to a first data buffer in the cache.