System and method for pre-encoding of data for direct write to multi-level cell memory

• US 9,400,713 B2
• Filed: 10/02/2014
• Issued: 07/26/2016
• Est. Priority Date: 10/02/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Gorobets, Sergey Anatolievich
• Primary Examiner(s): Ton, David
• Application Number:
  US14/505,291
• Publication Number:
  US 20160098319A1
• Time in Patent Office: 663 Days
• Field of Search: 714/773
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method and system for reducing data transfers between memory controller and multi-level cell (MLC) non-volatile memory during programming passes of a word line (WL) in the non-volatile memory. The system includes a controller and non-volatile memory having multiple WLs, each WL having a plurality of MLC memory cells. The controller stores received data in volatile memory until a target WL amount of data is received. The controller pre-encodes the received data into direct WL programming data for each programming pass necessary to program a target MLC WL. All direct WL programming data for all programming passes are stored in the volatile memory before programming. Different portions of direct WL programming data are transmitted from the controller to the non-volatile memory each pass. The received data may be deleted from the volatile memory before transmitting at least a portion of the direct WL programming data to the non-volatile memory.

Claims

1. A non-volatile memory system comprising:

a multi-level cell (MLC) non-volatile memory having a plurality word lines, each word line (WL) having a plurality of MLC memory cells and programmable in a plurality of programming passes; and

circuitry comprising;

volatile memory configured to receive, in a first portion, an amount of data from a data source, the amount of received data corresponding to a storage capacity of a word line (WL) in the MLC non-volatile memory;

a pre-encoding engine configured to convert the amount of received data in the first portion into direct WL programming data for all of the plurality of programming passes to be performed in one of the plurality of word lines, and to store the direct WL programming data for all of the plurality of programming passes for the one of the plurality of wordlines in a second portion of the volatile memory; and

a processor configured to transmit a different portion of the direct WL programming data from the second portion to the one of the plurality of wordlines for each of the plurality of programming passes.

2. The non-volatile memory system of claim 1, wherein the circuitry further comprises an error correction code (ECC) engine in communication with the volatile memory and the pre-encoding engine, the ECC engine positioned to apply an error correction code to the amount of received data prior to the pre-encoding engine converting the amount of received data.

3. The non-volatile memory system of claim 2, further comprising:

a data scrambling engine in communication with the ECC engine and configured to rearrange an order of data after application of an error correction code in the ECC engine and prior to the pre-encoding engine converting the amount of received data to direct WL programming data.

4. The non-volatile memory system of claim 2, wherein the pre-encoding engine comprises a data structure, and wherein the pre-encoding engine is configured to look up a set of direct WL programming bits in the data structure associated with each set of bits in the received data.

5. The non-volatile memory system of claim 1, wherein the data source comprises a host device, the first portion of the volatile memory comprises a portion of a random access memory (RAM) and the RAM is configured to receive data from the host device for programming to the MLC non-volatile memory.

6. The non-volatile memory system of claim 1, wherein the data source comprises a portion of the MLC non-volatile memory, the first portion of the volatile memory comprises a portion of a random access memory (RAM) and the RAM is configured to receive data from the portion of the MLC non-volatile memory for programming to the one of the plurality of word lines as part of an off-chip copy operation.

7. The non-volatile memory system of claim 1, further comprising a single level cell (SLC) non-volatile memory in communication with the processor, wherein the processor is configured to, in response to detecting an interruption prior to completion of the plurality of programming passes, transmit the direct WL programming data currently stored in the second portion of the volatile memory to the SLC non-volatile memory.

8. The non-volatile memory system of claim 7, wherein the interruption comprises a power shutdown.

9. The non-volatile memory system of claim 1, further comprising a single level cell (SLC) non-volatile memory in communication with the processor, wherein the controller is configured to first transmit all of the direct WL programming data stored in the second portion of the volatile memory to the SLC non-volatile memory, and to then transfer from the SLC non-volatile memory to the one of the plurality of word lines in the MLC non-volatile memory only a portion of the direct WL programming data configured for a particular programming pass of the plurality of programming passes to the MLC non-volatile memory until the particular programming pass is complete.

10. The non-volatile memory system of claim 1, wherein the MLC non-volatile memory comprises a die having a plurality of memory cells forming a monolithic three-dimensional structure.

11. A method of operating a non-volatile memory system comprising:

in a non-volatile memory system having a multi-level cell (MLC) non-volatile memory having a plurality word lines, each word line (WL) having a plurality of MLC memory cells, and a controller in communication with the MLC non-volatile memory and a volatile memory;

receiving data from a data source;

storing the received data in a first portion of the volatile memory until a predetermined amount of data has been received, the predetermined amount comprising an amount of data corresponding to a storage capacity of a word line (WL) in the MLC non-volatile memory;

converting the predetermined amount of received data into direct WL programming data for each of a plurality of programming passes to be performed in the MLC non-volatile memory for one of the plurality of word lines;

storing the direct WL programming data for all of the plurality of programming passes for the one of the plurality of word lines in a second portion of the volatile memory; and

for each of the plurality of programming passes for the one of the plurality of word lines, transmitting from the second portion of the volatile memory an amount of direct WL programming data that is less than the predetermined amount of data received.

12. The method of claim 11, further comprising, after storing the direct WL programming data for the plurality of programming passes, only transmitting a portion of the direct WL programming data configured for a particular programming pass of the plurality of programming passes to the MLC non-volatile memory until the particular programming pass is complete.

13. The method of claim 11, wherein the data source comprises a host device and the volatile memory comprises random access memory (RAM), and wherein receiving data comprises:

receiving data from the host device for programming to the MLC non-volatile memory; and

storing the received data in the RAM.

14. The method of claim 11, wherein the data source comprises a portion of the MLC non-volatile memory and receiving data comprises receiving data from the portion of the MLC non-volatile memory for programming to a different portion of the MLC non-volatile memory as part of an off-chip copy operation.

15. The method of claim 11, further comprising, in response to detecting an interruption prior to completion of the plurality of programming passes, transmitting the direct WL programming data stored in the second portion of the volatile memory to a single level cell (SLC) non-volatile memory.

16. The method of claim 15, wherein the interruption comprises a power shutdown or a volatile memory flush.

17. The method of claim 11, further comprising:

transmitting all of the direct WL programming data stored in the second portion of the volatile memory to a single level cell (SLC) non-volatile memory; and

transferring, from the SLC non-volatile memory to the one of the plurality of word lines in the MLC non-volatile memory, only a portion of the direct WL programming data configured for a particular programming pass of the plurality of programming passes to the MLC non-volatile memory until the particular programming pass is complete.

18. The method of claim 11, wherein converting the predetermined amount of received data into direct WL programming data further comprises the controller:

generating error correction code data for each page of received data;

scrambling the received data and associated error correction code data to rearrange an order of data bits in the received data and generated error correction code data into scrambled data; and

converting the scrambled data into one or more pages of direct WL programming data for each of the plurality of programming passes.

19. The method of claim 18, wherein converting the scrambled data comprises determining a set of direct WL programming bits associated with each set of bits in the scrambled data from a data structure in the memory system containing predetermined sets of direct WL programming bits mapped to corresponding scrambled data bit patterns.

20. A non-volatile memory system comprising:

a multi-level cell (MLC) non-volatile memory having a plurality word lines, each word line (WL) having a plurality of MLC memory cells and programmable in a plurality of programming passes; and

circuitry comprising;

volatile memory configured to receive, in a first portion, an amount of received data from a data source, the amount of received data corresponding to a storage capacity of a word line (WL) in the MLC non-volatile memory;

a pre-encoding engine configured to convert the amount of received data in the first portion into direct WL programming data for all of the plurality of programming passes to be performed in one of the plurality of word lines, and to store the direct WL programming data for all of the plurality of programming passes for the one of the plurality of wordlines in a second portion of the volatile memory; and

a processor configured to delete the amount of received data from the volatile memory before transmitting at least a portion of the direct WL programming data to the MLC non-volatile memory from the volatile memory.