Physical address management in solid state memory

• US 9,400,745 B2
• Filed: 11/06/2013
• Issued: 07/26/2016
• Est. Priority Date: 11/06/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Camp, Charles J., Fisher, Timothy J., Sallese, Kevin E.
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US14/073,614
• Publication Number:
  US 20150127922A1
• Time in Patent Office: 993 Days
• Field of Search: 711/103, 711/113, 711/165
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/651 Multi-level translation tables
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Claims

1. A storage system comprising:

a memory controller;

a read status table comprising;

a pending read indication and an associated physical address of a solid state memory device;

a physical address field comprising the physical address;

a read pending field comprising a count of pending reads associated with the physical address;

a valid field comprising an active entry if there are pending reads associated with the physical address or comprising an inactive entry if there are no pending reads associated with the physical address, and;

a write pending field comprising an active entry if the memory controller initiates a write to the physical address and if the valid field is inactive, the write pending field active entry indicates the physical address is an old physical address and is available to be released for reassignment;

and

wherein the memory controller connected to the solid state memory device releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address.

2. The storage system of claim 1 wherein the memory controller releases the physical address for reassignment further upon the memory controller initiating a pending write to the physical address.

3. The storage system of claim 2 further comprising:

a translation table that associates a first logical address to the physical address, and;

a reassignment engine that assigns a second logical address to the physical address subsequent to the memory controller releasing the physical address.

4. The storage system of claim 1 wherein the pending read indication is a pending read count.

5. The storage system of claim 1 wherein the memory controller releases the physical address for reassignment further upon the memory controller determining the physical address is an old physical address.

6. The storage system of claim 1 further comprising:

a tag index table that is an index to the read status table, the tag index table comprising a plurality of tag address entries associated with a plurality of read status table pointers.

7. A memory controller for controlling reading and writing of data from or to a solid state memory device comprising:

a read status table comprising;

a pending read indication and an associated physical address of a solid state memory device;

a physical address field comprising the physical address;

a read pending field comprising a count of pending reads associated with the physical address;

a valid field comprising an active entry if there are pending reads associated with the physical address or comprising an inactive entry if there are no pending reads associated with the physical address, and;

a write pending field comprising an active entry if the memory controller initiates a write to the physical address and if the valid field is inactive, the write pending field active entry indicates the physical address is an old physical address and is available to be released for reassignment;

and

wherein the memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address.

8. The memory controller of claim 7 wherein the memory controller releases the physical address for reassignment further upon the memory controller initiating a pending write to the physical address.

9. The memory controller of claim 8 further comprising:

a translation table that associates a first logical address to the physical address, and;

a reassignment engine that assigns a second logical address to the physical address subsequent to the memory controller releasing the physical address.

10. The memory controller of claim 7 wherein the memory controller releases the physical address for reassignment further upon the memory controller determining the physical address is an old physical address.

11. The memory controller of claim 7 wherein the pending read indication is a pending read count.

12. The memory controller of claim 7 further comprising:

a tag index table that is an index to the read status table, the tag index table comprising a plurality of tag address entries associated with a plurality of read status table pointers.

13. A method for managing old physical addresses in a solid state memory device comprising:

tracking in a read status table a pending read from the solid state memory device and a physical address within the solid state memory device associated with the pending read;

read status table comprising;

a pending read indication and an associated physical address of a solid state memory device;

a physical address field comprising the physical address;

a read pending field comprising a count of pending reads associated with the physical address;

a valid field comprising an active entry if there are pending reads associated with the physical address or comprising an inactive entry if there are no pending reads associated with the physical address, and;

a write pending field comprising an active entry if the memory controller initiates a write to the physical address and if the valid field is inactive, the write pending field active entry indicates the physical address is an old physical address and is available to be released for reassignment;

and

releasing the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address.

14. The method of claim 13 further comprising:

assigning, with a memory controller for controlling reading and writing of data from or to the solid state memory device, a first logical address to the physical address, and;

assigning, with the memory controller, a second logical address to the physical address subsequent to the physical address being released.

15. The method of claim 13 wherein tracking in the read status table the pending read from the solid state memory device and the physical address within the solid state memory device associated with the pending read further comprises:

receiving, with a memory controller for controlling reading and writing of data from or to the solid state memory device, a read command and an associated logical address;

determining, with the memory controller, the physical address from the logical address, and;

querying, with the memory controller, the read status table for an entry associated with the physical address.

16. The method of claim 13 wherein tracking in the read status table the pending read from the solid state memory device and the physical address within the solid state memory device associated with the pending read further comprises:

populating, with the memory controller, a read pending entry in the read status table associated with the physical address.

17. The method of claim 16 wherein populating the read pending entry in the read status table further comprises:

incrementing, with the memory controller, a read pending count.

18. The method of claim 17 wherein tracking in the read status table the pending read from the solid state memory device and the physical address within the solid state memory device associated with the pending read further comprises:

decrementing, with the memory controller, the read pending count upon the completion of the read command.