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Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces

  • US 9,400,821 B2
  • Filed: 03/15/2013
  • Issued: 07/26/2016
  • Est. Priority Date: 10/02/2012
  • Status: Active Grant
First Claim
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1. A computer system comprising:

  • a plurality of computing nodes, wherein each computing node of the plurality of computing nodes includes one or more coprocessors, one or more central processing units (CPUs), and a memory directly coupled to the one or more coprocessors,wherein each memory of said each computing node resides in a separate and distinct physical domain;

    a plurality of point-to-point physical communications links coupling the plurality of computing nodes,wherein the one or more coprocessors of said each computing node interface directly with the one or more communications links to transfer data over the plurality of point-to-point physical communications link without involving the one or more CPUs of said each computing node,wherein a particular coprocessor of a particular node is configured to transfer data between the memory coupled to the particular coprocessor at the particular node and a first remote memory of a first remote node over the one or more communications links, without involving the one or more CPUs, using a first certificate that grants access to a portion of the memory in the first remote node,wherein the particular node is a destination node for the data transfer, the destination node including a persistent address space,wherein the destination node transmits an acknowledgment indicating that the transferred data resides in the persistent address space.

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