Non-volatile dynamic random access memory (NVDRAM)
First Claim
1. A non-volatile dynamic random access memory (NVDRAM), comprising:
- a first bit line;
a first non-volatile line;
a second non-volatile line;
a first select line; and
a first NVDRAM cell, comprising;
a first DRAM cell, coupled to the first bit line, comprising;
a first capacitor having a first terminal coupled to a first storage node and a second terminal coupled to a reference; and
a first transfer transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to the first storage node, and a control electrode;
a first pass gate transistor coupled between the first bit line and the first storage node;
a first non-volatile element having a first terminal coupled to the control electrode of the first transfer transistor and a second terminal coupled to the first non-volatile line;
a second non-volatile element having a first terminal coupled to the control electrode of the first transfer transistor and a second terminal;
a first switching transistor having a first current electrode for receiving a first program signal, a second current electrode coupled to the control electrode of the first transfer transistor, and a control electrode coupled to the first select line; and
a second switching transistor having a first current electrode coupled to the second terminal of the second non-volatile element, a second current electrode coupled to the second non-volatile line, and a control electrode coupled to the first select line.
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Accused Products
Abstract
A NVDRAM includes a first NV element coupled to a first terminal of a second NV element at a transfer node. A volatile cell has a transfer transistor coupled to the transfer node and has a storage node. A first NV line is coupled to the second terminal of the first NV element. Circuitry applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to a second NV line, and applies a program signal across the first and second NV lines during a program mode that establishes a logic state. The circuitry applies a read signal across the first and second NV lines, couples the second terminal of the second NV element to the second NV line, and replaces the alternated signal with floating during a restore mode that loads the logic state into the storage node.
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Citations
19 Claims
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1. A non-volatile dynamic random access memory (NVDRAM), comprising:
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a first bit line; a first non-volatile line; a second non-volatile line; a first select line; and a first NVDRAM cell, comprising; a first DRAM cell, coupled to the first bit line, comprising; a first capacitor having a first terminal coupled to a first storage node and a second terminal coupled to a reference; and a first transfer transistor having a first current electrode coupled to a first power supply terminal, a second current electrode coupled to the first storage node, and a control electrode; a first pass gate transistor coupled between the first bit line and the first storage node; a first non-volatile element having a first terminal coupled to the control electrode of the first transfer transistor and a second terminal coupled to the first non-volatile line; a second non-volatile element having a first terminal coupled to the control electrode of the first transfer transistor and a second terminal; a first switching transistor having a first current electrode for receiving a first program signal, a second current electrode coupled to the control electrode of the first transfer transistor, and a control electrode coupled to the first select line; and a second switching transistor having a first current electrode coupled to the second terminal of the second non-volatile element, a second current electrode coupled to the second non-volatile line, and a control electrode coupled to the first select line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a non-volatile dynamic random access memory (NVDRAM) cell having a first non-volatile element having a first terminal coupled to a first terminal of a second non-volatile element at a transfer node, the first and second non-volatile elements having second terminals, comprising:
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programming the first non-volatile element and the second non-volatile element by applying a voltage differential to the second terminals of the first and second non-volatile elements while providing an alternated voltage at the transfer node to result in a logic state represented by a resistance differential between the first non-volatile element and the second non-volatile element; transferring the logic state to a storage node through a transfer transistor coupled to the transfer node and the storage node; and reading the logic state by coupling the storage node to a bit line through a pass gate transistor. - View Dependent Claims (14, 15, 16, 17)
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18. A non-volatile dynamic random access memory (NVDRAM), comprising:
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a first non-volatile element having a first terminal coupled to a first terminal of a second non-volatile element at a transfer node, the first and second non-volatile elements having second terminals; a DRAM cell having a transfer transistor and a storage node, wherein the transfer transistor is coupled to the storage node and the transfer node; a first non-volatile line coupled to the second terminal of the first non-volatile element and a second non-volatile line; and circuitry that, during a program mode, applies an alternated signal to the transfer node, couples the second terminal of the second non-volatile element to the second non-volatile line, and applies a program signal across the first and second non-volatile lines and that, during a restore mode, applies a read signal across the first and second non-volatile lines, couples the second terminal of the second non-volatile element to the second non-volatile line, and replaces the alternated signal with floating, in which a logic state represented the first and second non-volatile elements that have been programmed is loaded from the transfer node to the storage node. - View Dependent Claims (19)
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Specification