Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating

• US 9,401,206 B2
• Filed: 04/07/2015
• Issued: 07/26/2016
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/680,268
• Publication Number:
  US 20150213892A1
• Time in Patent Office: 476 Days
• Field of Search: 365/148, 365/100
• US Class Current: 1/1
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0027 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 14/0036 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

Claims

1. A semiconductor memory array comprising:

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and

a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said floating body upon transfer thereto;

wherein said floating body has a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said memory cell further comprising first and second regions at first and second locations of said memory cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;

wherein said transfer is performed to said at least two of said memory cells in parallel.

2. The semiconductor memory array of claim 1, wherein said resistance change element comprises a material selected from at least one of:

transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

3. The semiconductor memory array of claim 1, wherein said bipolar resistive change element is electrically connected to said capacitorless transistor and a distance between said bipolar resistive change element and said capacitorless transistor, when electrically connected, is in the range from about 90 nm to 1 μ

m.

4. The semiconductor memory array of claim 1, wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

5. The semiconductor memory array of claim 4, wherein said bipolar resistive change element is electrically connected to said one of said first and second regions via a conductive element.

6. The semiconductor memory array of claim 4, further comprising an addressable line electrically connected to said bipolar resistive change element.

7. The semiconductor memory array of claim 6, wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.

8. The semiconductor memory array of claim 1, further comprising:

a substrate being made of a material having said second conductivity type; and

a buried layer in said substrate below said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

wherein said floating body of each said memory cell is formed between said first and second regions and said buried layer; and

wherein said non-volatile memory is electrically connected to one of said first and second regions.

9. The semiconductor memory array of claim 1, further comprising:

a substrate being made of a material having said second conductivity type;

a well in said substrate, said well having said first conductivity type; and

a buried layer located between said well and said first and second regions, spaced apart from said first and second regions and having said second conductivity type;

wherein said floating body of each said memory cell is formed between said first and second regions and said buried layer;

and wherein said non-volatile memory is electrically connected to one of said first and second regions.

10. An integrated circuit comprising:

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and

a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said floating body upon transfer thereto;

wherein said floating body has a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said memory cell further comprising first and second regions at first and second locations of said cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and

a circuitry to perform said transfer.

11. The integrated circuit of claim 10, wherein said transfer is performed to said at least two of said memory cells in parallel.

12. The semiconductor memory array of claim 10, wherein said resistance change element comprises a material selected from at least one of:

transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

13. The semiconductor memory array of claim 10, wherein said bipolar resistive change element is electrically connected to said capacitorless transistor and a distance between said bipolar resistive change element and said capacitorless transistor, when electrically connected, is in the range of from about 90 nm to 1 μ

m.

14. The semiconductor memory array of claim 10, wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

15. A semiconductor memory cell comprising:

a bipolar device configured to store data when power is applied to said cell; and

a nonvolatile memory comprising a bipolar resistive change element configured to store data stored in said bipolar device upon transfer thereto.

16. The semiconductor memory cell of claim 15, wherein said bipolar resistive change element comprises a material selected from at least one of:

transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

17. The semiconductor memory cell of claim 15, wherein said bipolar resistive change element is electrically connected to said bipolar device and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range of from about 90 nm to 1 μ

m.

18. The semiconductor memory cell of claim 15, wherein said bipolar device comprises a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said memory cell further comprising first and second regions at first and second locations of said memory cell, said first and second regions each having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and

wherein said bipolar resistive change element comprises an electrode and a bipolar resistive change material electrically connected to one of said first and second regions.

19. The semiconductor memory cell of claim 18, wherein said bipolar resistive change element is electrically connected to said one of said first and second regions via a conductive element.

20. The semiconductor memory cell of claim 15, further comprising an addressable line electrically connected to said bipolar resistive change element.