Air gaps structures for damascene metal patterning

• US 9,401,305 B2
• Filed: 11/05/2014
• Issued: 07/26/2016
• Est. Priority Date: 11/05/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Takahashi, Yuji, Futase, Takuya, Furihata, Yoko, Kamata, Satoshi
• Primary Examiner(s): Kraig, WIlliam F
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US14/533,839
• Publication Number:
  US 20160126130A1
• Time in Patent Office: 629 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A pattern of parallel lines defines first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being smaller than a predetermined distance, and defines second regions where conductive material is to be located, a distance between adjacent lines in the second regions being larger than the predetermined distance. A subsequent layer caps air gaps between lines in the first regions. Conductive material is then deposited and planarized to form lines of conductive material in the second regions.

Claims

1. A method of forming air gaps in an integrated circuit comprising:

forming a plurality of parallel lines of dielectric of equal height on a first layer of dielectric;

the plurality of parallel lines defining first regions where no conductive material is to be located, a distance between adjacent lines in the first regions being smaller than a predetermined distance;

the plurality of parallel lines defining second regions where conductive material is to be located, a distance between adjacent lines in the second regions being larger than the predetermined distance;

subsequently, depositing a second layer that caps air gaps between lines in the first regions that are less than the predetermined distance apart and that deposits the second layer on the first layer of dielectric in the second regions where adjacent lines are more than the predetermined distance apart;

subsequently removing the second layer in the second regions to expose the surface of the first layer;

subsequently depositing barrier metal and conductive material across the first and second regions; and

subsequently planarizing to expose the second layer in the first regions and to form individual lines of conductive material in the second regions.

4. The method of claim 1 wherein the forming of the plurality of parallel lines comprises:

forming a third layer on the first layer of dielectric;

forming a mask pattern on the third layer using a lithography process; and

forming the plurality of line patterns from the third layer by patterning the third layer using the mask pattern and an anisotropic etch process.

5. The method of claim 1 wherein the second layer has a first thickness in the first regions and a second thickness in the second regions, the first thickness being greater than the second thickness.

6. The method of claim 1 wherein the bather metal is a metal that has a significant etch rate when etching dielectric material.

7. The method of claim 6 wherein the barrier metal is titanium.

8. The method of claim 1 wherein the planarizing exposes the second layer in the first regions where the second layer overlies air gaps, and wherein the planarizing does not expose the air gaps.

2. The method of claim I wherein the forming of the plurality of parallel lines comprises:

forming a third layer on the first layer of dielectric, the third layer formed of a material with a lower etching rate than the first layer;

patterning the third layer to form core portions;

depositing a fourth layer on top surfaces of the core portions, side walls of the core portions, and on a surface of the first layer;

etching back the fourth layer to remove the fourth layer from the top surfaces of the core portions to expose the top surfaces of the core portions and to remove the fourth layer from the surface of the first layer; and

removing the core portions while maintaining the fourth layer that was deposited on the sidewalls of the core portions.

3. The method of claim 2 wherein the core portions have a tapered shape with bottom surface in contact with the first layer of dielectric, the bottom surface being wider than the top surface.

9. A method of forming metal lines in an integrated circuit comprising:

forming a plurality of air gap mandrels on a dielectric layer;

fanning sidewalls on the plurality of air gap mandrels;

subsequently, removing the plurality of air gap mandrels;

subsequently, depositing a capping layer to enclose a plurality of air gaps where the plurality of air gap mandrels were removed; and

subsequently depositing bit line metal to form a plurality of bit lines at locations between the plurality of air gaps.

10. The method of claim 9 further comprising forming large areas without metal by forming a plurality of elongated closely-spaced air gap mandrels in the large areas so that the capping layer forms a continuous covering over tops of sidewalls formed on the plurality of elongated closely-spaced air gap mandrels.

11. The method of claim 10 further comprising enclosing additional air gaps in the large areas, the additional air gaps formed between sidewalls formed on neighboring mandrels of the plurality of elongated closely-spaced air gap mandrels.

12. The method of claim 11 further comprising, prior to depositing the bit line metal, etching back the capping layer to remove the capping layer at locations where the capping layer is in contact with the dielectric layer without exposing the plurality of air gaps or the additional air gaps.

13. The method of claim 9 further comprising planarizing the bit line metal to separate bit lines at locations between the plurality of air gaps.

14. The method of claim 13 wherein the planarizing of the bit line metal to separate bit lines also planarizes the capping layer and the planarizing stops at a level above the plurality of air gaps so that air gaps remain enclosed.

15. The method of claim 13 wherein, subsequent to depositing the bit line metal to form the plurality bit lines, the bit liens are not exposed to any etching.