Dual layer stack for contact formation

• US 9,401,336 B2
• Filed: 11/04/2014
• Issued: 07/26/2016
• Est. Priority Date: 11/04/2014
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arvin, Charles L., Cox, Harry D., Erwin, Brian M., Knickerbocker, Sarah H., McLaughlin, Karen P., Russell, David J.
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US14/532,764
• Publication Number:
  US 20160126201A1
• Time in Patent Office: 630 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03612 by physical means only
• CPC Class Codes: H01L 2224/03614 by chemical means only
• CPC Class Codes: H01L 2224/0381 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11474 Multilayer masks
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/1181 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/119 Methods of manufacturing bump connectors involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13157 : Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/1316 : Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/13164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.

Claims

1. A semiconductor device fabrication method comprising:

forming a liner layer upon a dielectric layer;

forming an electrically conductive plating layer upon the liner layer;

forming an epoxy trench barrier layer upon the plating layer;

forming a photoresist layer upon the epoxy trench barrier layer;

forming a contact trench within the photoresist layer and the epoxy trench barrier layer,

wherein the formed contact trench creates photoresist layer portions and epoxy trench barrier layer portions, and wherein the contact trench exposes a portion of the electrically conductive plating layer;

plating a contact upon the exposed plating layer within the contact trench, and;

subsequent to plating the contact upon the plating layer within the contact trench,

removing the photoresist layer portions while maintaining the epoxy trench barrier layer portions.

2. The semiconductor device fabrication method of claim 1, further comprising:

subsequent to removing the photoresist layer portions, removing the epoxy trench barrier layer portions to expose the electrically conductive plating layer thereunder.

3. The semiconductor device fabrication method of claim 1, further comprising:

removing portions of the electrically conductive plating layer exterior to the contact, such that sidewalls of the electrically conductive plating layer are coplanar with sidewalls the contact.

4. The semiconductor device fabrication method of claim 1, further comprising:

removing portions of the liner layer exterior to the contact, such that sidewalls of the liner layer are coplanar with sidewalls the contact.

5. The semiconductor device fabrication method of claim 1, wherein the contact is a pillar.

6. The semiconductor device fabrication method of claim 1, wherein the contact trench is formed by removing a section of the photoresist layer and removing a section of the epoxy trench barrier layer with a single etchant.

7. The semiconductor device fabrication method of claim 1, wherein the photoresist layer and epoxy trench barrier layer have a similar toned photosensitivity.

8. The semiconductor device fabrication method of claim 1, wherein the epoxy barrier layer portions protect the electrically conductive plating layer thereunder from corrosion from metal species within a photoresist stripping solution utilized to remove the photoresist layer portions.

9. A semiconductor device fabrication method comprising:

forming a liner layer upon a dielectric layer;

forming an electrically conductive plating layer upon the liner layer;

forming an organic material (OM) trench barrier layer upon the plating layer;

forming a photoresist layer upon the OM trench barrier layer;

forming a contact trench within the photoresist layer and the OM trench barrier layer, wherein the formed contact trench creates photoresist layer portions and OM trench barrier layer portions, and wherein the contact trench exposes a portion of the electrically conductive plating layer;

plating a contact upon the exposed plating layer within the contact trench, and;

subsequent to plating the contact upon the plating layer within the contact trench, removing the photoresist layer portions while maintaining the OM trench barrier layer portions.

10. The semiconductor device fabrication method of claim 9, further comprising:

subsequent to removing the photoresist layer portions, removing the OM trench barrier layer portions to expose the electrically conductive plating layer thereunder.

11. The semiconductor device fabrication method of claim 9, further comprising:

removing portions of the electrically conductive plating layer exterior to the contact, such that sidewalls of the electrically conductive plating layer are coplanar with sidewalls the contact.

12. The semiconductor device fabrication method of claim 9, further comprising:

removing portions of the liner layer exterior to the contact, such that sidewalls of the liner layer are coplanar with sidewalls the contact.

13. The semiconductor device fabrication method of claim 9, wherein the contact is a pillar.

14. The semiconductor device fabrication method of claim 9, wherein the contact trench is formed by removing a section of the photoresist layer and removing a section of the OM trench barrier layer with a single etchant.

15. The semiconductor device fabrication method of claim 9, wherein the photoresist layer and OM trench barrier layer have a similar toned photosensitivity.

16. The semiconductor device fabrication method of claim 9, wherein the OM barrier layer portions protect the electrically conductive plating layer thereunder from corrosion from metal species within a photoresist stripping solution utilized to remove the photoresist layer portions.

17. The semiconductor device fabrication method of claim 9, wherein electrically conductive plating layer is copper and wherein the OM barrier layer is an organic solderability preservative that selectively bonds to the conductive plating layer.