Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices

• US 9,401,363 B2
• Filed: 08/23/2011
• Issued: 07/26/2016
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wang, Kuo Chen, Manavalan, Sriraj, Liao, Wei Ming
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US13/215,981
• Publication Number:
  US 20130049110A1
• Time in Patent Office: 1,799 Days
• Field of Search: 257/296, 257/302, 257/329, 257/E27.096, 438/138, 438/212, 438/268
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

Claims

1. A vertical transistor device, comprising:

a line of active area adjacent a line of dielectric isolation;

a buried data/sense line obliquely angling relative to the line of active area and the line of dielectric isolation;

a pair of gate lines outward of the buried data/sense line and obliquely angling relative to the line of active area and the line of dielectric isolation, a vertical transistor channel region within the active area between the pair of gate lines; and

an outer source/drain region in the active area above the channel region and an inner source/drain region in the active area below the channel region, the inner source/drain region being electrically coupled to the buried data/sense line, the inner source/drain region extending to under a base of the buried data/sense line and being directly against the base of the buried data/sense line.

2. The device of claim 1 wherein the pair of gate lines are parallel one another.

3. The device of claim 2 wherein the buried data/sense line is perpendicular relative to the pair of gate lines.

4. The device of claim 1 wherein the data/sense and gate lines are longitudinally straight.

5. The device of claim 1 wherein the inner source/drain region is directly against a sidewall of the buried data/sense line.

7. The device of claim 1 wherein the outer source/drain region has an outer target contact area having a trapezoidal shaped perimeter considered horizontally.

8. The device of claim 1 wherein the outer source/drain region has an outer target contact area having a pentagonal shaped perimeter considered horizontally.

9. The device of claim 1 comprising a charge storage component electrically coupled to the outer source/drain region.

10. The device of claim 9 wherein the charge storage component is directly against the outer source/drain region and directly against the dielectric isolation.

11. The device of claim 9 wherein,

the charge storage component is directly against the outer source/drain region;

the outer source/drain region has an outer target contact area having a trapezoidal shaped perimeter considered horizontally or a pentagonal shaped perimeter considered horizontally; and

the charge storage component is directly against only a portion of the outer target contact area.

12. The device of claim 1 wherein the line of active area comprises a first line of active area and further comprising a second line of active area, the first and second lines of active area being on opposing sides of the line of dielectric isolation, the buried data/sense line being directly against each of the first and second lines of active area.

13. The device of claim 1 wherein the line of active area comprises a first line of active area and further comprising a second line of active area, the first and second lines of active area being on opposing sides of the line of dielectric isolation, and further comprising semiconductive material beneath and interconnecting the first and second lines of active area, the buried data/sense line having a base directly against the semiconductive material.

14. The device of claim 13 wherein the buried data/sense line comprises opposing sides individually directly against one of the first and second lines of active area.

6. A vertical transistor device, comprising:

a line of active area adjacent a line of dielectric isolation;

an individual buried data/sense line obliquely angling relative to the line of active area and the line of dielectric isolation;

a pair of gate lines outward of the buried data/sense line and obliquely angling relative to the line of active area and the line of dielectric isolation, a vertical transistor channel region within the active area between the pair of gate lines; and

an outer source/drain region in the active area above the channel region and an inner source/drain region in the active area below the channel region, the inner source/drain region being electrically coupled to the buried data/sense line, the inner source/drain region being directly against two opposing sidewalls of the individual buried data/sense line, wherein the inner source/drain region extends to under a base of the individual buried data/sense line and is directly against the base of the individual buried data/sense line.

15. A plurality of vertical transistor devices, comprising:

lines of active area alternating with lines of dielectric isolation;

buried data/sense lines obliquely angling relative to the lines of active area and the lines of dielectric isolation;

pairs of gate lines outward of the buried data/sense lines and obliquely angling relative to the lines of active area and the lines of dielectric isolation, an individual vertical transistor channel region within the active area between the gate lines of individual pairs of the gate lines, gate dielectric being between individual of the gate lines and individual of the channel regions, the gate dielectric extending elevationally inward deeper than do the gate lines; and

pairs of outer and inner source/drain regions in the active area above and below, respectively, the individual channel regions;

the inner source/drain regions individually being electrically coupled to individual buried data/sense lines, the inner source/drain regions comprising pairs of immediately laterally adjacent inner source/drain regions, and further comprising a doped isolation region within the lines of active area between and separating immediately adjacent of the pairs of immediately laterally adjacent inner source/drain regions, individual of the doped isolation regions being beneath and directly against an elevationally innermost surface of the gate dielectric.

16. The devices of claim 15 wherein the lines of active area and dielectric isolation are longitudinally straight.

17. The devices of claim 15 wherein the gate lines within the pairs of gate lines are parallel and longitudinally straight relative one another.

18. The devices of claim 17 wherein the buried data/sense lines are perpendicular relative to the pairs of gate lines.

19. The devices of claim 15 wherein the inner source/drain regions are directly against the individual buried data/sense lines.

20. The devices of claim 19 wherein the inner source/drain regions are directly against a sidewall of the individual buried data/sense lines.

25. The devices of claim 15 wherein the inner source/drain regions extend to under a respective base of individual of the buried data/sense lines and are directly against the respective base of the individual buried data/sense lines.

21. A plurality of vertical transistor devices, comprising:

lines of active area alternating with lines of dielectric isolation;

buried data/sense lines obliquely angling relative to the lines of active area and the lines of dielectric isolation;

pairs of gate lines outward of the buried data/sense lines and obliquely angling relative to the lines of active area and the lines of dielectric isolation, an individual vertical transistor channel region within the active area between the gate lines of individual pairs of the gate lines;

pairs of outer and inner source/drain regions in the active area above and below, respectively, the individual channel regions;

the inner source/drain regions individually being electrically coupled to individual buried data/sense lines, the inner source/drain regions comprising pairs of immediately laterally adjacent inner source/drain regions, and further comprising a doped isolation region within the lines of active area between and separating immediately adjacent of the pairs of immediately laterally adjacent inner source/drain regions; and

some of the outer source/drain regions having respective outer target contact areas having a trapezoidal shaped perimeter considered horizontally and another some of the outer source/drain regions have respective outer target contact areas having a pentagonal shaped perimeter considered horizontally.

22. A memory array, comprising:

lines of active area alternating with lines of dielectric isolation;

buried data/sense lines obliquely angling relative to the lines of active area and the lines of dielectric isolation;

pairs of gate lines outward of the buried data/sense lines and obliquely angling relative to the lines of active area and the lines of dielectric isolation, an individual vertical transistor channel region within the active area between the gate lines of individual pairs of the gate lines, gate dielectric being between individual of the gate lines and individual of the channel regions, the gate dielectric extending elevationally inward deeper than do the gate lines;

pairs of outer and inner source/drain regions in the active area above and below, respectively, the individual channel regions;

the inner source/drain regions individually being electrically coupled to individual buried data/sense lines, the inner source/drain regions comprising pairs of immediately laterally adjacent inner source/drain regions, and further comprising a doped isolation region within the lines of active area between and separating immediately adjacent of the pairs of immediately laterally adjacent inner source/drain regions, individual of the doped isolation regions being beneath and directly against an elevationally innermost surface of the gate dielectric; and

individual charge storage components electrically coupled to individual outer source/drain regions.

23. The memory array of claim 22 wherein the charge storage components are capacitors and the memory array comprises DRAM.

24. The memory array of claim 22 wherein the inner source/drain regions are directly against the individual buried data/sense lines.

26. The memory array of claim 22 wherein the inner source/drain regions extend to under a respective base of individual of the buried data/sense lines and are directly against the respective base of the individual buried data/sense lines.

27. A vertical transistor device, comprising:

a line of active area adjacent a line of dielectric isolation;

a buried data/sense line obliquely angling relative to the line of active area and the line of dielectric isolation;

a pair of gate lines outward of the buried data/sense line and obliquely angling relative to the line of active area and the line of dielectric isolation, a vertical transistor channel region within the active area between the pair of gate lines; and

an outer source/drain region in the active area above the channel region and an inner source/drain region in the active area below the channel region, the inner source/drain region being electrically coupled to the buried data/sense line, the inner source/drain region being directly against two opposing sidewalls of the buried data/sense line, the inner source/drain region being between the channel region and the buried data/sense line, the inner source/drain region extending to under a base of the buried data/sense line.

28. The device of claim 27 wherein the inner source/drain region is directly against the channel region.

29. The device of claim 27 wherein the inner source/drain region is directly against the base of the buried data/sense line.

30. A plurality of vertical transistor devices, comprising:

lines of active area alternating with lines of dielectric isolation;

buried data/sense lines obliquely angling relative to the lines of active area and the lines of dielectric isolation;

pairs of gate lines outward of the buried data/sense lines and obliquely angling relative to the lines of active area and the lines of dielectric isolation, an individual vertical transistor channel region within the active area between the gate lines of individual pairs of the gate lines; and

pairs of outer and inner source/drain regions in the active area above and below, respectively, the individual channel regions;

the inner source/drain regions individually being electrically coupled to individual buried data/sense lines, the inner source/drain regions comprising pairs of immediately laterally adjacent inner source/drain regions, and further comprising a doped isolation region within the lines of active area between and separating immediately adjacent of the pairs of immediately laterally adjacent inner source/drain regions, individual of the doped isolation regions extending elevationally inward deeper than do each of a) the buried data/sense lines, and b) the inner source/drain regions.

31. A memory array, comprising:

lines of active area alternating with lines of dielectric isolation;

buried data/sense lines obliquely angling relative to the lines of active area and the lines of dielectric isolation;

pairs of gate lines outward of the buried data/sense lines and obliquely angling relative to the lines of active area and the lines of dielectric isolation, an individual vertical transistor channel region within the active area between the gate lines of individual pairs of the gate lines;

pairs of outer and inner source/drain regions in the active area above and below, respectively, the individual channel regions;

the inner source/drain regions individually being electrically coupled to individual buried data/sense lines, the inner source/drain regions comprising pairs of immediately laterally adjacent inner source/drain regions, and further comprising a doped isolation region within the lines of active area between and separating immediately adjacent of the pairs of immediately laterally adjacent inner source/drain regions, individual of the doped isolation regions extending elevationally inward deeper than do each of a) the buried data/sense lines, and b) the inner source/drain regions; and

individual charge storage components electrically coupled to individual outer source/drain regions.