Decoupling MIM capacitor designs for interposers and methods of manufacture thereof

• US 9,401,395 B2
• Filed: 02/05/2016
• Issued: 07/26/2016
• Est. Priority Date: 08/12/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tzeng, Kuo-Chyuan, Tu, Kuo-Chi, Wang, Chen-Jong, Lee, Hsiang-Fan
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US15/017,059
• Publication Number:
  US 20160155700A1
• Time in Patent Office: 172 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

Claims

1. A device comprising:

an interposer, the interposer comprising;

a substrate;

a first metallization layer over the substrate and a second metallization layer over the first metallization layer;

a capacitor in the second metallization layer, the capacitor comprising a bottom electrode, a dielectric over the bottom electrode, and a top electrode over the dielectric; and

a first contact pad electrically coupled to the bottom electrode; and

an integrated circuit die, wherein the capacitor is electrically coupled between the integrated circuit die and the first contact pad.

2. The device of claim 1, wherein the interposer further comprises a through via, wherein the capacitor is electrically coupled between the integrated circuit die and the through via.

3. The device of claim 1, further comprising a first via layer interposed between the first metallization layer and the second metallization layer.

4. The device of claim 3, wherein the bottom electrode extends through the first via layer.

5. The device of claim 4, further comprising a conductive interconnect, the conductive interconnect comprising a first conductive line in the second metallization layer and a first conductive via extending through the first via layer.

6. The device of claim 1, further comprising a top plate pick-up, wherein the top plate pick-up extends into the second metallization layer.

7. The device of claim 1, wherein the interposer is free of active devices.

8. A device comprising:

an interposer substrate;

a first dielectric layer over the interposer substrate;

a second dielectric layer over the first dielectric layer;

a first electrode in the second dielectric layer and extending through the first dielectric layer;

a capacitor dielectric over the first electrode in the first dielectric layer and the second dielectric layer;

a second electrode over the capacitor dielectric in the first dielectric layer and the second dielectric layer;

a first via extending through the first dielectric layer;

a first conductive line extending through the second dielectric layer, the first conductive line coupled to the first via; and

an integrated circuit die electrically coupled to the first conductive line, the first conductive line being interposed between the integrated circuit die and the interposer substrate.

9. The device of claim 8, wherein the first electrode does not extend to an upper surface of the second dielectric layer.

10. The device of claim 8, wherein the second electrode extends over a top surface of the second dielectric layer.

11. The device of claim 10, further comprising a top plate pickup in the second dielectric layer.

12. The device of claim 11, wherein the second electrode extends laterally over the second dielectric layer to the top plate pickup.

13. The device of claim 8, wherein an upper surface of the second dielectric layer is level with an upper surface of the second electrode and the capacitor dielectric.

14. The device of claim 13, wherein the upper surface of the second dielectric layer is level with an upper surface of the first electrode.

15. The device of claim 8, wherein the second electrode comprises a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer completely fills an area interposed between opposing sidewalls of the capacitor dielectric.

16. The device of claim 8, further comprising a third dielectric layer over the second electrode, wherein the third dielectric layer extends into the second dielectric layer.

17. A device comprising:

an interposer, the interposer comprising;

an interposer substrate;

a plurality of dielectric layers on a first side of the interposer substrate;

contact pads on a second side of the interposer substrate;

a capacitor extending through at least a first dielectric layer and a second dielectric layer of the plurality of dielectric layers; and

an interconnect extending through the first dielectric layer and the second dielectric layer, the interconnect comprising a via extending through the first dielectric layer and a conductive line extending through the second dielectric layer.

18. The device of claim 17, wherein the capacitor comprises:

a first electrode extending along sidewalls and a bottom of an opening in the first dielectric layer and the second dielectric layer, the first electrode not extending to an upper surface of the second dielectric layer;

a capacitor dielectric layer over the first electrode, the capacitor dielectric layer extending to the upper surface of the second dielectric layer; and

a second electrode over the capacitor dielectric layer, the second electrode extending to the upper surface of the second dielectric layer.

19. The device of claim 17, wherein the capacitor comprises:

a first electrode extending along sidewalls and a bottom of an opening in the first dielectric layer and the second dielectric layer;

a capacitor dielectric layer over the first electrode; and

a second electrode over the capacitor dielectric layer, upper surfaces of the first electrode, the capacitor dielectric layer, and the second electrode being level with an upper surface of the second dielectric layer.

20. The device of claim 17, wherein the capacitor comprises:

a first electrode extending along sidewalls and a bottom of an opening in the first dielectric layer and the second dielectric layer;

a capacitor dielectric layer over the first electrode, the capacitor dielectric layer extending over an upper surface of the second dielectric layer; and

a second electrode over the capacitor dielectric layer, the second electrode extending over an upper surface of the second dielectric layer.