High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

• US 9,401,424 B2
• Filed: 07/08/2014
• Issued: 07/26/2016
• Est. Priority Date: 10/20/2003
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Dokumaci, Omer H., Chen, Huajie, Chidambarrao, Dureseti
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/325,540
• Publication Number:
  US 20140322873A1
• Time in Patent Office: 749 Days
• Field of Search: 438/230
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a field effect transistor structure on a substrate;

forming spacers on respective sidewalls of the field effect transistor structure;

forming a protection layer over a top surface of the field effect transistor structure, after forming the spacers;

removing the protection layer from over the top surface of the field effect transistor structure;

forming a stressing layer on the substrate, the stressing layer comprising a first lattice constant different from a second lattice constant of the substrate;

doping the stressing layer with dopants; and

forming a silicide layer on the stressing layer.

2. The method of claim 1, wherein:

the first lattice constant of the stressing layer comprises a larger lattice constant than the second lattice constant of the substrate;

the stressing layer comprises a SiGe layer; and

the dopants comprise p-type dopants.

3. The method of claim 1, wherein:

the first lattice constant of the stressing layer comprises a smaller lattice constant than the second lattice constant of the substrate;

the stressing layer comprises a SiC layer; and

the dopants comprise n-type dopants.

4. The method of claim 1, further comprising:

etching the substrate adjacent the field effect transistor structure, to provide an etched region of the substrate,

wherein the stressing layer is formed in the etched region of the substrate.

5. The method of claim 4, wherein forming the protection layer comprises forming the protection layer to a thickness range of approximately 5 to 20 nm over the field effect transistor structure prior to etching the substrate.

6. The method of claim 5, further comprising:

etching a portion of the protection layer to expose the substrate adjacent the field effect transistor structure, wherein the protection layer comprises an insulating layer comprising Silicon and Nitrogen.

7. The method of claim 1, wherein forming the protection layer comprises forming the protection layer on the stressing layer.

8. A method of forming a semiconductor device, the method comprising:

forming a pFET stack and a nFET stack on a substrate;

forming spacers on respective sidewalls of the pFET stack and the nFET stack;

forming a protection layer over respective top surfaces of the pFET stack and the nFET stack, and over the spacers;

forming a first stressing layer adjacent the pFET stack, the first stressing layer comprising a first lattice constant larger than a second lattice constant of the substrate;

forming a second stressing layer adjacent the nFET stack;

doping the first stressing layer with p-type dopants;

doping the second stressing layer with n-type dopants; and

forming silicide layers on each of the first and second stressing layers.

9. The method of claim 8, wherein the second stressing layer comprises a third lattice constant smaller than the second lattice constant of the substrate.

10. The method of claim 8, further comprising:

removing a portion of the protection layer that is over the pFET stack before forming the first stressing layer adjacent the pFET stack.

11. The method of claim 10, wherein the protection layer comprises a first protection layer, the method further comprising:

forming a second protection layer on the first stressing layer and over the pFET stack and the nFET stack.

12. The method of claim 11, further comprising:

removing a portion of the second protection layer prior to forming the second stressing layer.

13. The method of claim 8, wherein:

the first stressing layer comprises a SiGe layer, and

the second stressing layer comprises a SiC layer.

14. The method of claim 8, wherein forming the second stressing layer comprises:

forming a second mask on the pFET stack and exposing the nFET stack;

etching the substrate at opposing sides of the nFET stack to form an etched region; and

selectively growing the second stressing layer within the etched region,

wherein the doping of the second stressing layer is performed before removing the second mask.

15. The method of claim 8, further comprising:

forming an isolation region between the pFET stack and the nFET stack, and in the substrate,

wherein forming the protection layer comprises forming the protection layer on the isolation region.

16. A method of forming a semiconductor device, the method comprising:

forming a pFET stack and a nFET stack on a substrate;

forming a first stressing layer adjacent the pFET stack, the first stressing layer comprising a first lattice constant larger than a second lattice constant of the substrate, wherein forming the first stressing layer comprises;

forming a first mask on the nFET stack and exposing the pFET stack;

etching the substrate, while the first mask is on the nFET stack, to form a trench at opposing sides of the pFET stack; and

selectively growing the first stressing layer within the trench;

forming a second stressing layer adjacent the nFET stack;

doping the first stressing layer with p-type dopants;

doping the second stressing layer with n-type dopants; and

forming silicide layers on each of the first and second stressing layers.

17. The method of claim 16, further comprising:

removing the first mask after doping the first stressing layer.

18. The method of claim 16, further comprising forming an isolation region in the substrate, wherein forming the first mask comprises forming the first mask on a first portion of the isolation region but not on a second portion of the isolation region.