Apparatus and method for improving power supply rejection ratio

• US 9,401,679 B1
• Filed: 05/01/2015
• Issued: 07/26/2016
• Est. Priority Date: 05/01/2015
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Vijaykumar, Sharad
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US14/702,586
• Time in Patent Office: 452 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 1/14 by use of neutralising means
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/308 using MOSFET
• CPC Class Codes: H03F 2200/121 A transistor in common gate configuration being used in a feedback circuit of an amplifier stage
• CPC Class Codes: H03F 2200/135 there being a feedback over one or more internal stages in the global amplifier
• CPC Class Codes: H03F 2200/141 the feedback circuit of the amplifier stage comprising a resistor and a capacitor in series, at least one of them being an active one
• CPC Class Codes: H03F 2200/144 the feedback circuit of the amplifier stage comprising a passive resistor and passive capacitor
• CPC Class Codes: H03F 2200/153 Feedback used to stabilise the amplifier
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/75 the amplifier stage being a common source configuration MOSFET
• CPC Class Codes: H03F 2203/30018 A series coupled active resistor and capacitor are coupled in a feedback circuit of a SEPP amplifier
• CPC Class Codes: H03F 2203/30021 A capacitor being coupled in a feedback circuit of a SEPP amplifier
• CPC Class Codes: H03F 2203/30033 A series coupled resistor and capacitor are coupled in a feedback circuit of a SEPP amplifier
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 2203/45281 One SEPP output stage being added to the differential amplifier
• CPC Class Codes: H03F 2203/45632 the LC comprising one or more capacitors coupled to the LC by feedback
• CPC Class Codes: H03F 2203/45648 the LC comprising two current sources, which are not cascode current sources
• CPC Class Codes: H03F 2203/45682 the LC comprising one or more op-amps
• CPC Class Codes: H03F 2203/45692 the LC comprising one or more resistors in series with a capacitor coupled to the LC by feedback
• CPC Class Codes: H03F 2203/45698 : the LC comprising one or more resistors coupled to the LC by feedback (active or passive)
• CPC Class Codes: H03F 2203/45708 : the LC comprising one SEPP circuit as output stage
• CPC Class Codes: H03F 3/3022 : CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45192 : Folded cascode stages
• CPC Class Codes: H03F 3/45273 : Mirror types
• CPC Class Codes: H03F 3/45475 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45744 : by offset reduction

Abstract

A compensation capacitor can be added to an amplifier for stability. Disclosed are systems and methods for improving the power supply rejection ratio (PSRR) performance of an amplifier in the presence of one or more compensation capacitors.

Claims

1. An apparatus comprising:

a first output transistor of an amplifier, wherein the first output transistor is electrically coupled to an output node;

an amplifier compensation circuit comprising a compensation capacitor and an isolating transistor, wherein;

the compensation capacitor has a first end and a second end, wherein the first end is electrically coupled to the output node, wherein the second end is electrically coupled to a first node;

a source and a drain of the isolating transistor are in a conductive path between the first node and a gate of the first output transistor; and

a biasing transistor in series with the isolating transistor, wherein the biasing transistor is configured to bias the isolating transistor, wherein the biasing transistor is part of a current mirror load of a first stage of the amplifier;

wherein the isolating transistor is biased by diverting a first current from the first stage of the amplifier and returning the first current to the first stage of the amplifier.

2. The apparatus of claim 1 wherein the amplifier compensation circuit further comprises a second compensation capacitor and a second isolating transistor, wherein:

the second compensation capacitor has a first end and a second end, wherein the first end of the second compensation capacitor is electrically coupled to the output node, wherein the second end of the second compensation capacitor is electrically coupled to a second node;

a source and a drain of the second isolating transistor are in a conductive path between the second node and a gate of a second output transistor; and

a second biasing transistor in series with the second isolating transistor, wherein the second biasing transistor is configured to bias the second isolating transistor, wherein the second biasing transistor is part of a second current mirror load of the first stage of the amplifier;

wherein the second isolating transistor is biased by diverting a second current from the first stage of the amplifier and returning the second current to the first stage of the amplifier.

3. The apparatus of claim 2 further comprising a voltage source circuit configured to bias the gates of the first and second isolating transistors with a reference voltage that is substantially invariable to voltage fluctuations of a power supply of the amplifier.

4. The apparatus of claim 2 wherein the biasing transistor is part of a current mirror load of the first stage of the amplifier such that a size ratio of the biasing transistor, a first transistor of the current mirror load and a second transistor of the current mirror load is about 2 to 3 to 5 respectively.

5. The apparatus of claim 2 wherein the second biasing transistor is part of a second current mirror load of the first stage of the amplifier such that a size ratio of the second biasing transistor, a first transistor of the second current mirror load and a second transistor of the second current mirror load is about 2 to 3 to 5 respectively.

6. The apparatus of claim 2 further comprising:

first and second stability capacitors, wherein;

the first stability capacitor has a first end and a second end, wherein the first end of the first stability capacitor is electrically coupled to the first node and the second end of the first stability capacitor is electrically coupled to a source of the first biasing transistor; and

the second stability capacitor has a first end and a second end, wherein the first end of the second stability capacitor is electrically coupled to the second node and the second end of the second stability capacitor is electrically coupled to a source of the second biasing transistor.

7. The apparatus of claim 2 further comprising:

first and second stability capacitors, wherein;

the first stability capacitor has a first end and a second end, wherein the first end of the first stability capacitor is electrically coupled to the first node and the second end of the first stability capacitor is electrically coupled to the gate of the first or the second output transistor; and

the second stability capacitor has a first end and a second end, wherein the first end of the second stability capacitor is electrically coupled to the second node and the second end of the second stability capacitor is electrically coupled to the gate of the first or the second output transistor.

8. The apparatus of claim 2 wherein the amplifier comprises a class AB amplifier.

9. The apparatus of claim 8 further comprising a class AB control circuit wherein:

the control circuit comprises a first control transistor and a second control transistor.

10. An electrically implemented method of amplifier compensation, the method comprising:

electrically coupling a first output transistor of an amplifier, to an output node;

electrically coupling a first end of a compensation capacitor to the output node, and electrically coupling a second end of the compensation capacitor to a first node;

electrically coupling a source and a drain of an isolating transistor in a conductive path between the first node and a gate of the first output transistor;

biasing the isolating transistor with a biasing transistor in series with the isolating transistor;

mirroring a current from a current mirror load of a first stage of the amplifier to the biasing transistor; and

diverting a first current from the first stage of the amplifier and returning the first current to the first stage of the amplifier.

11. The method of claim 10 further comprising:

electrically coupling a first end of a second compensation capacitor to the output node, and electrically coupling a second end of the second compensation capacitor to a second node;

electrically coupling a source and a drain of a second isolating transistor in a conductive path between the second node and a gate of a second output transistor;

biasing the second isolating transistor with a second biasing transistor in series with the second isolating transistor;

mirroring a second current from a second current mirror load of the first stage of the amplifier to the second biasing transistor; and

diverting a second current from the first stage of the amplifier and returning the second current to the first stage of the amplifier.

12. The method of claim 11 further comprising:

biasing, with a voltage source circuit, the gates of the first and second isolating transistors with a reference voltage that is substantially invariable to voltage fluctuations of a power supply of the amplifier.

13. The method of claim 11 wherein the biasing transistor is part of a current mirror load of the first stage of the amplifier such that a size ratio of the biasing transistor, a first transistor of the current mirror load and a second transistor of the current mirror load is about 2 to 3 to 5 respectively.

14. The method of claim 11 wherein the second biasing transistor is part of a second current mirror load of the first stage of the amplifier such that a size ratio of the second biasing transistor, a first transistor of the second current mirror load and a second transistor of the second current mirror load is about 2 to 3 to 5 respectively.

15. The method of claim 11 further comprising:

providing first and second stability capacitors,

electrically coupling a first end of the first stability capacitor to the first node, and electrically coupling a second end of the first stability capacitor to a source of the biasing transistor; and

electrically coupling a first end of the second stability capacitor to the second node, and electrically coupling a second end of the second stability capacitor to a source of the second biasing transistor.

16. The method of claim 11 further comprising:

providing first and second stability capacitors,

electrically coupling a first end of the first stability capacitor to the first node, and electrically coupling a second end of the first stability capacitor to the gate of the first or the second output transistor or mp7; and

electrically coupling a first end of the second stability capacitor to the second node, and electrically coupling a second end of the second stability capacitor to the gate of the first or the second output transistor.

17. The method of claim 11 wherein:

the amplifier comprises a class AB amplifier.

18. The method of claim 17 wherein:

the amplifier further comprises a class AB control circuit, wherein the control circuit comprises;

a first control transistor and a second control transistor.

19. An apparatus comprising:

means for outputting an output of an amplifier to an output node;

means for compensation, wherein a first end of the compensation means is configured to be electrically coupled to the output node, and a second end of the compensation means is configured to be electrically coupled to a first node;

means for isolating the output node, wherein the isolating means is in a conductive path between the first node and a gate terminal of the outputting means;

means for biasing the isolating means, wherein the biasing means is in series with the isolating means;

means for mirroring a first current to the biasing means; and

means for diverting the first current from a first stage of the amplifier and returning the first current to the first stage of the amplifier.

20. The apparatus of claim 19 further comprising:

second means for outputting the output of the amplifier to the output node;

second means for compensation, wherein a first end of the second compensation means is configured to be electrically coupled to the output node, and a second end of the second compensation means is configured to be electrically coupled to a second node;

second means for isolating the output node, wherein the second isolating means is in a conductive path between the second node and a gate terminal of the second outputting means;

second means for biasing the second isolating means in series with the second isolating means;

second means for mirroring a second current to the second biasing means; and

means for diverting the second current from a first stage of the amplifier and returning the second current to the first stage of the amplifier.