Wireless communication link using near field coupling

• US 9,401,745 B1
• Filed: 12/11/2009
• Issued: 07/26/2016
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Abdulla, Mostafa Naguib
• Primary Examiner(s): Talukder, Md
• Application Number:
  US12/635,961
• Time in Patent Office: 2,419 Days
• Field of Search: 455/41.1, 455/41.2, 455/41.3, 455/558, 455/73, 455/90.3
• US Class Current: 1/1
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1434 Memory
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 7/00 Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• CPC Class Codes: H01Q 7/005 with variable reactance for tuning the antenna
• CPC Class Codes: H04B 5/00 : Near-field transmission systems, e.g. inductive or capacitive transmission systems
• CPC Class Codes: H04B 5/26 : using coils
• CPC Class Codes: H04B 5/48 : Transceivers
• CPC Class Codes: H04B 5/72 : for local intradevice communication

Abstract

A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field coupling.

Claims

1. A method comprising:

enabling a memory integrated circuit to communicate wirelessly with a first neighboring memory integrated circuit over a first frequency, wherein the memory integrated circuit includes a physical electrical connection to the first neighboring memory integrated circuit, wherein the physical electrical connection provides signals other than those provided wirelessly, wherein the memory integrated circuit includes;

a substrate having an upper surface and a lower surface opposite to and distinct from the upper surface;

a first loop antenna on the upper surface;

a second loop antenna on the lower surface;

a third loop antenna formed within the substrate parallel and adjacent to an edge of the substrate;

wherein a portion of the third antenna extends over the upper surface and is coupled to a portion of the third antenna within the substrate by a first via and a second via extending through the substrate; and

a plurality of connectors coupled to the lower surface;

coupling an integrated circuit chip to the upper surface within a perimeter defined by the first antenna, wherein the integrated circuit chip is configured to tune frequencies of the first, second, or third antennas;

coupling at least one of the first, second, or third antenna of the memory integrated circuit to an antenna of the first neighboring memory integrated circuit, wherein the at least one antenna is within a near field region of the antenna of the first neighboring memory integrated circuit to reduce interference from other antennas, wherein the at least one antenna is coupled to the memory integrated circuit by wire bonds;

enabling the memory integrated circuit to communicate wirelessly with a second neighboring memory integrated circuit over a second frequency; and

coupling at least one of the first, second, or third antenna of the memory integrated circuit to an antenna of the second neighboring memory integrated circuit, wherein the at least one antenna is within the near field region of the antenna second neighboring memory integrated circuit to reduce interference from other antennas, wherein the at least one antenna coupled to the antenna of the second neighboring memory integrated circuit is different than the at least one antenna coupled to the antenna of the first neighboring memory integrated circuit.

2. The method of claim 1, further comprising forming at least one array of memory integrated circuits arranged generally in a plane.

3. The method of claim 2, further comprising arranging at least three of the at least one memory integrated circuit arrays in parallel planes, wherein each memory integrated circuit of each of the at least three memory integrated circuit arrays is configured to communicate wirelessly with each neighboring memory integrated circuit, wherein each neighboring memory integrated circuit communicates at a different frequency, wherein antennas of each neighboring memory integrated circuit configured to communicate wirelessly are in parallel planes.

4. The method of claim 3, further comprising forming physical electrical connections between neighboring memory integrated circuits of each of the at least three memory integrated circuit arrays.

5. The method of claim 1, further comprising forming an array of memory integrated circuits spaced from one another at a distance of approximately one millimeter.

6. The method of claim 1, further comprising forming a plurality of memory integrated circuits, each of the plurality of memory integrated circuits having a corresponding length and corresponding width, wherein a distance between adjacent memory integrated circuits is less than the corresponding length and the corresponding width of either of the adjacent memory integrated circuits.

7. The method of claim 1, further comprising providing at least one of a power signal or a reference signal from the memory integrated circuit to the first neighboring memory integrated circuit via the physical electrical connection.

8. The method of claim 1, further comprising:

coupling the integrated circuit chip to the first, second, or third antennas by wire bonds.

9. The method of claim 8, further comprising tuning the first, second, or third antennas to different frequencies.

10. The method of claim 1, wherein forming the first antenna includes plating of a conductive strip on the upper surface.

11. An apparatus comprising:

a substrate having an upper surface, a lower surface different from the upper surface, a first short edge, a second short edge, a first long edge, and a second long edge, wherein the edges define a perimeter of the substrate;

a first loop antenna on the upper surface and configured to couple to an antenna of a first memory integrated circuit adjacent to the upper surface;

a second loop antenna on the lower surface and configured to couple to an antenna of a second memory integrated circuit adjacent to the lower surface;

a third loop antenna formed within the substrate parallel to the first short edge and configured to couple to an antenna of a third memory integrated circuit adjacent to the first short edge;

a fourth loop antenna formed within the substrate parallel to the second short edge and configured to couple to an antenna of a fourth memory integrated circuit adjacent to the second short edge;

a fifth loop antenna formed within the substrate parallel to the first long edge and configured to couple to an antenna of a fifth memory integrated circuit adjacent to the first long edge;

a sixth loop antenna formed within the substrate parallel to the second long edge and configured to couple to an antenna of a sixth memory integrated circuit adjacent to the second long edge;

wherein a portion of each of the third, fourth, fifth, and sixth loop antennas extend over the upper surface and is coupled to a respective portion of the third, fourth, fifth, and sixth loop antennas within the substrate by a plurality of vias extending through the substrate;

a plurality of connectors coupled to the lower surface; and

an integrated circuit chip coupled to the upper surface within a perimeter defined by the first loop antenna, wherein the integrated circuit chip is further coupled to the first, second, third, fourth, fifth, and sixth loop antennas by wire bonds, wherein the integrated circuit chip is configured to tune frequencies of the loop antennas.

12. The apparatus of claim 11, wherein the integrated circuit chip includes a control and power amplifier coupled to a first and a second capacitor, wherein the first and second capacitor are coupled in parallel, wherein the second capacitor is tunable.

13. The apparatus of claim 11, wherein the first loop antenna is configured to couple to an additional loop antenna parallel to the first loop antenna, wherein the additional loop antenna is on a lower surface of the first memory integrated circuit positioned above the apparatus.

14. The apparatus of claim 11, wherein the first loop antenna is a plating of a conductive strip on the upper surface.

15. The apparatus of claim 11, wherein the apparatus is included in an array of apparatuses coupled by wire bonds, wherein the apparatuses are further configured to pass signals by electromagnetic radiation through loop antennas, wherein the loop antennas are in parallel planes, wherein the wire bonds provide signals between the apparatuses other than those provided by electromagnetic radiation.

16. The apparatus of claim 15, wherein the array of apparatuses is a three dimensional array.

17. The apparatus of claim 15, wherein the array of apparatuses is configured such that spacing between the apparatus and the first memory integrated circuit in the array is less than a dimension of the apparatuses.

18. The apparatus of claim 13, wherein the first loop antenna is coupled to the additional loop antenna by near field coupling.