Systems and methods for sending and receiving information via a network device

• US 9,401,879 B1
• Filed: 06/23/2015
• Issued: 07/26/2016
• Est. Priority Date: 10/26/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Klemin, Bruce A., Alston, Jerald K., Rohde, Derek J.
• Primary Examiner(s): Scheibel, Robert C
• Application Number:
  US14/747,790
• Time in Patent Office: 399 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/356 for storage area networks
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 63/0485 Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

Abstract

A network device is provided. The network device includes a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving information complying with different protocols. The network device further includes a processor complex having a plurality of processors for processing information complying with different protocols and received by the plurality of ports; and a message queuing system (MQS) for managing messages for the plurality of processors regarding the received information complying with different protocols. Each processor can process information complying with any of the different protocols.

Claims

1. An adapter coupled to a host computing device for sending and receiving information, comprising:

a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving frames complying with different protocols, where the plurality of ports send frames on behalf of the host computing device and receive frames from other devices;

a processor complex having a plurality of processors for processing frames complying with different protocols and received by any of the plurality of ports;

wherein each processor of the processor complex can process frames complying with any of the different protocols and originating from any of the plurality of ports;

a message queuing system (MQS) interfacing with the port complex and the processor complex for managing messages for the plurality of processors regarding the received frames complying with different protocols such that any processor can process any message regardless of the protocol type;

wherein each message includes a standard information regardless of frame protocol and protocol specific information; and

a memory interface module that manages requests from any processor of the processor complex to access a local adapter memory and a host computing device memory for processing received frames and transmitting frames.

2. The adapter of claim 1, wherein the plurality of ports are configured to send and receive information complying with Ethernet, Fibre Channel, Fibre Channel over Ethernet (FCoE), Internet Small Computer Systems Interface (iSCSI), and remote direct memory access over converged Ethernet (RoCE) protocols.

3. The adapter of claim 1, wherein the adapter includes a first parser that initially parses a frame received by the plurality of ports by performing an initial checksum and determining a cyclic redundancy code.

4. The adapter of claim 3, wherein the first parser acquires encryption information when the frame is encrypted.

5. The adapter of claim 4, wherein the encrypted frame is sent to a decryption module that decrypts the encrypted frame and routes the decrypted frame for further processing.

6. The adapter of claim 3, wherein the first parser places the frame for further processing at a temporary memory storage having a plurality of memory storage locations.

7. The adapter of claim 3, further comprising:

a scheduler that selects the frame from a temporary memory storage location and forwards the frame to a second parser for further processing.

8. The adapter of claim 7, wherein the second parser generates a message associated with the frame for one of the plurality of processors and provides the message to the MQS.

9. The adapter of claim 8, wherein the message includes a first portion in a standard format regardless of a frame type and a second portion which is based on the frame type.

10. The adapter of claim 9, wherein the frame type includes an Ethernet frame type, a Fibre Channel frame type, a Fibre Channel over Ethernet frame type, an Internet Small Computer Systems Interface (iSCSI) frame type, and a remote direct memory access over converged (RoCE) frame type.

11. An adapter coupled to a host computing device for sending and receiving information, comprising:

a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving frames complying with different protocols, where the plurality of ports send frames on behalf of the host computing device and receive frames from other devices;

a first parser that initially parses a frame received by one of the plurality of ports by performing an initial checksum and determining a cyclic redundancy code and places the frame for further processing at a temporary memory storage having a plurality of memory storage locations;

a scheduler selects the frame from the temporary memory storage location and forwards the frame to a second parser that generates a message associated with the frame for one of a plurality of processors;

wherein each processor can process information complying with any of the different protocols and originating from any of the plurality of ports;

a message queuing system (MQS) interfacing with the port complex for managing messages for the plurality of processors regarding received frames complying with different protocols such that any processor can process any message regardless of the protocol type;

wherein each message includes standard information regardless of frame protocol type and protocol specific information; and

a memory interface module that manages requests from any processor to access a local adapter memory and a host computing device memory for processing received frames and transmitting frames.

12. The adapter of claim 11, wherein the message generated by the second parser includes a first portion in a standard format regardless of a frame type and a second portion which is based on the frame type.

13. The adapter of claim 12, wherein the frame type includes an Ethernet frame type, a Fibre Channel frame type, a Fibre Channel over Ethernet frame type, an Internet Small Computer Systems Interface (iSCSI) frame type, and a remote direct memory access over converged (RoCE) frame type.

14. The adapter of claim 11, wherein when the frame is encrypted, the first parser acquires encryption information regarding the frame, and the encrypted frame is sent to a decryption module that decrypts the encrypted frame and routes the decrypted frame for further processing.

15. An adapter coupled to a host computing device for sending and receiving information, comprising:

a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving frames complying with different protocols, where the plurality of ports send frames on behalf of the host computing device and receive frames from other devices;

a first parser that initially parses a frame received by one of the plurality of ports by performing an initial checksum and determining a cyclic redundancy code and places the frame for further processing at a temporary memory storage having a plurality of memory storage locations;

a scheduler that selects the frame from the temporary memory storage location and forwards the frame to a second parser that generates a message associated with the frame for one of a plurality of processors;

wherein each processor can process information complying with any of the different protocols and originating from any of the plurality of ports and wherein the message includes standard information regardless of frame protocol and protocol specific information; and

a memory interface module that manages requests from any processor to access a local adapter memory and a host computing device memory for processing received frames and transmitting frames.

16. The adapter of claim 15, wherein the message generated by the second parser includes a first portion in a standard format regardless of a frame type and a second portion which is based on the frame type.

17. The adapter of claim 16, wherein the frame type includes an Ethernet frame type, a Fibre Channel frame type, a Fibre Channel over Ethernet frame type, an Internet Small Computer Systems Interface (iSCSI) frame type, and a remote direct memory access over converged (RoCE) frame type.

18. The adapter of claim 15, wherein when the frame is encrypted, the first parser acquires encryption information regarding the frame, and the encrypted frame is sent to a decryption module that decrypts the encrypted frame and routes the decrypted frame for further processing.

19. The adapter of claim 15, further comprising:

a message queuing system (MQS) for managing messages for the plurality of processors regarding the frames complying with different protocols.