Method and apparatus for writing data to a flash memory

• US 9,405,485 B2
• Filed: 06/30/2014
• Issued: 08/02/2016
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Silicon Motion Technology Corporation
• Original Assignee: Silicon Motion Technology Corporation
• Inventors: Lee, Chun-Kun, Hsiao, Wei-Yi
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US14/319,990
• Publication Number:
  US 20140317341A1
• Time in Patent Office: 764 Days
• Field of Search: 711/103, 711/156, 365/185.12, 365/189.02, 365/200
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Claims

1. A method for managing flash memory data, comprising:

determining an address for transmitting data by a host, wherein the address is an original destination address;

waiting for the host to transmit the data to an external buffer;

determining whether the data in the external buffer have a first time transmission trait;

responsive to the data having the first time transmission trait, determining whether the address assigned by the host is a temporary address;

responsive to the assigned address being a temporary address, reading temporary data in the temporary address to the external buffer; and

executing a write command to reassign a new destination address,

wherein determining whether the data in the external buffer have a first time transmission trait comprises a determination as to whether the data is new.

2. The method of claim 1, further comprising:

writing the temporary data in the external buffer to a flash memory buffer.

3. The method of claim 2, further comprising:

writing the data transmitted from the host in the external buffer to the flash memory buffer,

wherein the data in the flash memory buffer have the original or new destination address.

4. The method of claim 1, wherein, if the data in the external buffer do not have the first time transmission trait, directly writing the data transmitted from the host in the external buffer to the flash memory buffer.

5. The method of claim 1, wherein, when the data in the external buffer have the first time transmission trait and the host assigned data transmission address is not the temporary address, executing an algorithm and then writing the data transmitted from the host in the external buffer to the flash memory buffer.

6. The method of claim 5, wherein the algorithm organizes the data in the external buffer so that the data becomes continuous.

7. The method of claim 3, further comprising:

determining whether writing host data to the external buffer has stopped.

8. The method of claim 7, further comprising:

responsive to a determination that the writing host data to the external buffer has stopped, determining whether the flash memory buffer is full and, if it is, writing the data to a destination block.

9. The method of claim 8, wherein, if the flash memory buffer is determined to be not full, assigning a temporary block to the data and writing the data into the temporary block.

10. The method of claim 7, further comprising:

responsive to a determination that the writing host data to the external buffer has not stopped, determining whether the flash memory buffer is full and, if it is, writing the data according to the destination address.

21. The method of claim 1, wherein if the address corresponding to the data is not the same as other addresses corresponding to other data stored in the external buffer, or is not located in the address range of the other data stored in the external buffer, the data is determined to have a first time transmission trait.

11. An apparatus for managing flash memory data, comprising:

at least one processor; and

at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following;

determine an address for transmitting data by a host, wherein the address is an original destination address;

wait for the host to transmit the data to an external buffer;

determine whether the data in the external buffer have a first time transmission trait;

responsive to the data having the first time transmission trait, determine whether the address assigned by the host is a temporary address;

responsive to the assigned address being a temporary address, read temporary data in the temporary address to the external buffer; and

execute a write command to reassign a new destination address,

wherein determining whether the data in the external buffer have a first time transmission trait comprises a determination as to whether the data is new.

12. The apparatus of claim 11, wherein the apparatus is further configured to:

write the temporary data in the external buffer to a flash memory buffer.

13. The apparatus of claim 12, wherein the apparatus is further configured to:

write the data transmitted from the host in the external buffer to the flash memory buffer,

wherein the data in the flash memory buffer have the original or new destination address.

14. The apparatus of claim 11, wherein, if the data in the external buffer do not have the first time transmission trait, the apparatus is configured to directly write the data transmitted from the host in the external buffer to the flash memory buffer.

15. The apparatus of claim 11, wherein, when the data in the external buffer have the first time transmission trait and the host assigned data transmission address is not the temporary address, the apparatus is configured to execute an algorithm and then write the data transmitted from the host in the external buffer to the flash memory buffer.

16. The apparatus of claim 15, wherein the algorithm organizes the data in the external buffer so that the data becomes continuous.

17. The apparatus of claim 13, wherein the apparatus is further configured to:

determine whether writing host data to the external buffer has stopped.

18. The apparatus of claim 17, wherein the apparatus is further configured to:

responsive to a determination that the writing host data to the external buffer has stopped, determine whether the flash memory buffer is full and, if it is, write the data to a destination block.

19. The apparatus of claim 18, wherein, if the flash memory buffer is determined to be not full, the apparatus is configured to assign a temporary block to the data and write the data into the temporary block.

20. The system of claim 17, wherein the apparatus is further configured to:

responsive to a determination that the writing host data to the external buffer has not stopped, determine whether the flash memory buffer is full and, if it is, write the data according to the destination address.