Prioritizing instructions based on the number of delay cycles
First Claim
1. An apparatus, comprising:
- an instruction-grouping circuit configured to organize a plurality of instructions for a computer processor into a plurality of instruction groups prior to execution;
a plurality of execution units configured to execute the plurality of instruction groups based upon cycles of a clock signal;
a delay-identification circuit including;
a delay counter that is configured to count a number of cycles occurring in a time period for a first group of instructions of the plurality of instruction groups, wherein the time period is an amount of time between when a group of instructions is ready to be dispatched to one or more execution units of the plurality of execution units and when the group of instructions has been completely executed by the one or more execution units;
a threshold register that is configured to store a threshold number of cycles that represents an undesired amount of delay within the time period;
a delay register that is configured to store at least one effective address of at least one instruction in the first group of instructions;
a delay detector circuit that is configured to;
detect when the first group of instructions is delayed in the time period;
in response to detecting that the first group of instructions is delayed, start the delay counter to count the number of cycles in the time period;
in response to detecting that the first group of instructions is no longer delayed, stop the delay counter;
compare the number of cycles counted with the threshold number of cycles; and
in response to determining the number of cycles counted is greater than the threshold number of cycles, store at least one effective address of at least one instruction of the first group of instructions; and
a group completion table that is configured to store data regarding the first group of instructions when the first group of instructions has been dispatched to the one or more execution units but has not been at least one of;
completely executed by the one or more execution units and flushed from the apparatus;
wherein the delay detector circuit is further configured to;
detect when the first group of instructions is delayed from being dispatched to the one or more execution units; and
detect when the group completion table is empty for one or more cycles; and
wherein the delay-identification circuit communicates a frequency, from among at least a first frequency and a second frequency, for processing the first group of instructions via the one or more execution units in response to anticipating a delay in the first group of instructions.
1 Assignment
0 Petitions
Accused Products
Abstract
Methods, systems, and computer program products may provide delay-identification in data processing systems. An apparatus may include a delay-identification unit having a delay counter, a threshold register, a delay register, and a delay detector. The delay detector may be configured to start the delay counter in response to detecting that one group of instructions is delayed, and stop the delay counter in response to detecting that the one group of instructions is no longer delayed. The delay detector may additionally be configured to compare the number of cycles counted by the delay counter with a threshold number of cycles in the threshold register, and store at least one effective address of one of the instructions of the one group of instructions when the number of cycles counted by the delay counter is greater than the threshold number of cycles stored in the threshold register.
14 Citations
17 Claims
-
1. An apparatus, comprising:
-
an instruction-grouping circuit configured to organize a plurality of instructions for a computer processor into a plurality of instruction groups prior to execution; a plurality of execution units configured to execute the plurality of instruction groups based upon cycles of a clock signal; a delay-identification circuit including; a delay counter that is configured to count a number of cycles occurring in a time period for a first group of instructions of the plurality of instruction groups, wherein the time period is an amount of time between when a group of instructions is ready to be dispatched to one or more execution units of the plurality of execution units and when the group of instructions has been completely executed by the one or more execution units; a threshold register that is configured to store a threshold number of cycles that represents an undesired amount of delay within the time period; a delay register that is configured to store at least one effective address of at least one instruction in the first group of instructions; a delay detector circuit that is configured to; detect when the first group of instructions is delayed in the time period; in response to detecting that the first group of instructions is delayed, start the delay counter to count the number of cycles in the time period; in response to detecting that the first group of instructions is no longer delayed, stop the delay counter; compare the number of cycles counted with the threshold number of cycles; and in response to determining the number of cycles counted is greater than the threshold number of cycles, store at least one effective address of at least one instruction of the first group of instructions; and a group completion table that is configured to store data regarding the first group of instructions when the first group of instructions has been dispatched to the one or more execution units but has not been at least one of;
completely executed by the one or more execution units and flushed from the apparatus;wherein the delay detector circuit is further configured to; detect when the first group of instructions is delayed from being dispatched to the one or more execution units; and detect when the group completion table is empty for one or more cycles; and wherein the delay-identification circuit communicates a frequency, from among at least a first frequency and a second frequency, for processing the first group of instructions via the one or more execution units in response to anticipating a delay in the first group of instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method, comprising:
-
in response to anticipating a delay in a group of instructions, communicating a frequency by a delay-identifying apparatus from among at least a first frequency and a second frequency, for processing the group of instructions via one or more execution units; counting, by the delay-identifying apparatus, a number of cycles of a clock signal occurring in a time period in which the group of instructions is delayed, wherein the time period is the amount of time between when the group of instructions is ready to be dispatched for execution by the one or more execution units and when the group of instructions is completely executed by the one or more execution units and is thus no longer delayed; detecting when the group of instructions is delayed in the time period; comparing, by the delay-identifying apparatus, the counted number of cycles with a threshold number of cycles, wherein the threshold number of cycles represents an undesired amount of delay within the time period; in response to determining the counted number of cycles is greater than the threshold number of cycles, storing, in a memory, an effective address of each instruction of the group of instructions; detecting when the group of instructions is delayed from being dispatched to the one or more execution units; storing, to a group completion table, data regarding the group of instructions when the group of instructions has been dispatched to the one or more execution units but has not been at least one of;
completely executed by the one or more execution units and flushed from the apparatus;detecting when the group completion table is empty for one or more cycles; in response to detecting the group completion table is empty for the one or more cycles, starting a delay counter; and in response to detecting the group completion table is no longer empty, stopping the delay counter. - View Dependent Claims (11, 12, 13)
-
-
14. A computer program product for identifying delays in a first computer processor having one or more execution units, the computer program product comprising at least one non-transitory computer readable storage medium having computer readable program instructions embodied therein that when executed by a second computer processor, enables the second computer processor to:
-
in response to anticipating a delay in a group of monitored program instructions, communicate a frequency, from among at least a first frequency and a second frequency, for processing the group of monitored program instructions via the one or more execution units; count a number of cycles of a clock signal occurring in a time period in which the group of monitored program instructions is delayed, wherein the time period is an amount of time between when the group of monitored program instructions is ready to be dispatched for execution by the one or more execution units and when the group of monitored program instructions is completely executed by the one or more execution units, thus no longer delayed; detect when the group of monitored program instructions is delayed in the time period; compare the counted number of cycles with a threshold number of cycles, wherein the threshold number of cycles represents an undesired amount of delay within the time period; in response to determining the counted number of cycles is greater than the threshold number of cycles, store, in a memory, an effective address of each instruction of the group of monitored program instructions; detect when the group of monitored program instructions is delayed from being dispatched to the one or more execution units; store, to a group completion table, data regarding the group of monitored program instructions when the group of monitored program instructions has been dispatched to the one or more execution units but has not been at least one of;
completely executed by the one or more execution units and flushed from the apparatus;detect when the group completion table is empty for one or more cycles; in response to detecting the group completion table is empty for the one or more cycles, start a delay counter; and in response to detecting the group completion table is no longer empty, stop the delay counter. - View Dependent Claims (15, 16, 17)
-
Specification