System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
First Claim
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1. A method comprising:
- generating an escape route from a first node to a second node in a switch fabric, wherein the escape route is an alternate, non-desirable route from the first node to the second node that has a lower priority weight than a desirable route, wherein the escape route violates routing rules of the desirable route, and wherein the switch fabric includes a plurality of nodes and a plurality of links to form a plurality of routes; and
misrouting data from the first node to the second node in response to a link between the first and second nodes being inactive, wherein the escape route and misrouting provide fault tolerance to the switch fabric, and wherein said misrouting includes;
setting, when a node in a data path does not have a link path to the second node, a misrouting bit in a header associated with the data, wherein the misrouting bit indicates an identity of the node in the data path that does not have the link path to the second node.
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Abstract
A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
365 Citations
17 Claims
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1. A method comprising:
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generating an escape route from a first node to a second node in a switch fabric, wherein the escape route is an alternate, non-desirable route from the first node to the second node that has a lower priority weight than a desirable route, wherein the escape route violates routing rules of the desirable route, and wherein the switch fabric includes a plurality of nodes and a plurality of links to form a plurality of routes; and misrouting data from the first node to the second node in response to a link between the first and second nodes being inactive, wherein the escape route and misrouting provide fault tolerance to the switch fabric, and wherein said misrouting includes; setting, when a node in a data path does not have a link path to the second node, a misrouting bit in a header associated with the data, wherein the misrouting bit indicates an identity of the node in the data path that does not have the link path to the second node. - View Dependent Claims (2, 3, 5)
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4. A switch system, comprising:
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a plurality of nodes; a plurality of links associated with each node that connect the node to another node in the plurality of nodes to create a topology of a switch fabric configured to route data through the plurality of nodes; a management processor configured to control the routing of data through the switch fabric; at least one routing header processor configured to generate a routing frame header for an Ethernet frame packet based on a routing table, wherein the routing table includes a path cost and weights for each link to permit adaptive routing of data packets, and wherein the at least one routing header processor is further configured to check an adaptive register to determine whether to do adaptive or deterministic routing; and a content addressable memory device configured to store a lookup table, wherein a single entry in the lookup table includes four or more contiguous MAC addresses in a single row of the lookup table, and wherein the entry includes an encoded port identification number. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification