Flash memory controller with calibrated data communication

• US 9,405,678 B2
• Filed: 09/21/2015
• Issued: 08/02/2016
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared LeVan, Donnelly, Kevin S., Sidiropoulos, Stefanos, Stark, Donald C., Horowitz, Mark A., Yu, Leung, Vu, Roxanne, Kim, Jun, Garlepp, Bruno W., Ho, Tsyr-Chyang, Lau, Benedict Chung-Kwong
• Primary Examiner(s): Nguyen, Brian D
• Application Number:
  US14/859,991
• Publication Number:
  US 20160011973A1
• Time in Patent Office: 316 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Claims

1. A flash memory controller, comprising:

a bus interface to couple to a plurality of flash memory devices, the bus interface including a circuit to send at least one signal to individually address a selected flash memory device of the plurality of flash memory devices and store a device-specific value in a reference voltage register of the selected flash memory device; and

a transmitter to output a data signal to the selected flash memory device

wherein the device-specific value stored in the reference voltage register of the selected flash memory device controls a reference voltage used by a corresponding receiver circuit of the selected flash memory device, the receiver circuit to receive the data signal transmitted by the flash memory controller to the selected flash memory device.

2. The flash memory controller of claim 1, wherein the device-specific value stored in the reference voltage register of the selected flash memory device is determined during a calibration mode of operation of the selected flash memory device.

3. The flash memory controller of claim 1, wherein each of the plurality of flash memory devices includes a write offset register to store a device-specific offset value corresponding to a receive timing adjustment, and the corresponding receiver circuit of the selected flash memory device is configured to sample the received data signal with a timing offset corresponding to the device-specific offset value stored in the write offset register.

4. The flash memory controller of claim 1, wherein the device-specific value stored in the reference voltage register of the selected flash memory device is determined during a initialization mode of operation of the selected flash memory device.

5. The flash memory controller of claim 1, wherein each of the plurality of flash memory devices includes:

a read offset register to store a device-specific offset value corresponding to a transmit timing adjustment; and

,

a transmit circuit to transmit a data signal from a respective one of the plurality of flash memory devices to the flash memory controller with a timing offset corresponding to the device-specific offset value stored in the read offset register.

6. The flash memory controller of claim 5, wherein the device-specific offset value stored by the flash memory controller in the read offset register of the selected flash memory device is determined during a calibration mode of operation of the selected flash memory device.

7. The flash memory controller of claim 5, wherein each the plurality of flash memory devices includes a feedback loop circuit operable to produce at least one of a transmit clock signal coupled to a clock input of the transmit circuit and a receive clock signal coupled to a clock input of the receiver circuit.

8. The flash memory controller of claim 1, wherein each of the plurality of flash memory devices includes calibration circuitry operable in a calibration mode and comprising a phase detector, the phase detector of a respective one of the plurality of flash memory devices comprising:

a first input to receive a clock signal,

a second input to receive a calibration sequence via a signal path associated with transmitting write data between the flash memory controller and the respective one of the plurality of flash memory devices, and

an output to provide phase data representing a phase difference between the clock signal and the received calibration sequence to the flash memory controller; and

wherein the flash memory controller is configured to receive the phase data from the respective one of the plurality of flash memory devices.

9. The flash memory controller of claim 1, wherein each of the plurality of flash memory devices includes calibration circuitry operable in a calibration mode, the calibration circuitry including a first input to receive a clock signal and a second input to receive a calibration sequence via a signal path associated with transmitting write data between the flash memory controller and a respective one of the plurality of flash memory devices.

10. The flash memory controller of claim 9, wherein the flash memory controller is configured to provide a data pattern as the calibration sequence to the respective one of the plurality of flash memory devices.

11. The flash memory controller of claim 1, wherein each of the plurality of flash memory devices includes a feedback loop circuit operable to produce a receive clock signal coupled to a clock input of the receiver circuit.

12. A method of operating a flash memory controller coupled to a set of flash memory devices, the method comprising:

individually addressing, by the flash memory controller, at least one selected flash memory device in the set of flash memory devices;

storing, by the flash memory controller, and in the selected flash memory device of the set of flash memory devices, a device-specific value in a reference voltage register of the selected flash memory device; and

,

transmitting, by the memory controller, and to the selected flash memory device, a data signal, the selected flash memory device receiving the data signal using a reference voltage controlled by the device-specific value stored by the flash memory controller in the reference voltage register of the selected flash memory device.

13. The method of claim 12, further including, storing, by the flash memory controller, the device-specific value in the reference voltage register of each individual flash memory device during a calibration mode of operation.

14. The method of claim 12, wherein each individual flash memory device in the set of flash memory devices includes a write offset register to store a device-specific offset value corresponding to a receive timing adjustment, and each respective individual flash memory device samples the data signal with a timing offset corresponding to the device-specific offset value stored in the write offset register of each respective individual flash memory device.

15. The method of claim 14, including storing, by the flash memory controller, the device-specific offset value in the write offset voltage register of each flash memory device during a calibration mode of operation.

16. The method of claim 14, wherein within each individual flash memory device internally generates a receive clock signal using a timing feedback loop circuit, and the timing feedback loop circuit provides the receive clock signal to an input to a receiver circuit of the individual flash memory device.

17. The method of claim 12, wherein each individual flash memory device in the set of flash memory devices includes a transmit circuit and a read offset register to store a device-specific offset value corresponding to a transmit timing adjustment;

and

the method further includes, receiving, by the flash memory controller and from the transmit circuit of a respective individual flash memory device, a data signal according to a timing offset corresponding to the device-specific offset value stored in the read offset register of the respective individual flash memory device.

18. The method of claim 17, including storing, by the flash memory controller, the device-specific value in the read offset register of each individual flash memory device during a calibration mode of operation.

19. The method of claim 12, wherein each individual flash memory device in the set of flash memory devices includes calibration circuitry operable in a calibration mode, the method further including:

to each of the flash memory devices, while the respective flash memory device is operating in the calibration mode, transmitting, by the flash memory controller, a calibration sequence via a signal path associated with transmitting write data between the flash memory controller and the respective flash memory device; and

,

receiving, by the flash memory controller and from the respective flash memory device, phase data representing a phase difference between a clock signal and a received calibration sequence corresponding to the calibration sequence transmitted via the signal path associated with transmitting write data between the flash memory controller and the respective flash memory device.

20. An apparatus comprising

a flash memory controller to couple to a plurality of flash memory devices and to individually control one or more of the plurality of flash memory devices to set, in each flash memory device, a reference voltage register with a device-specific value, and to transmit a data signal to one or more of the individually controlled flash memory devices;

and,

wherein the device-specific value stored in the reference voltage register of the one or more of the plurality of flash memory devices controls a reference voltage used by a corresponding receiver circuit of the respective flash memory device when receiving the data signal transmitted by the memory controller to the one or more of the individually controlled flash memory devices.