Memory device debugging on host platforms

• US 9,405,717 B2
• Filed: 11/21/2013
• Issued: 08/02/2016
• Est. Priority Date: 11/21/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Brontvein, Gabi, Cohen, Inon, Gueta, Asaf
• Primary Examiner(s): Wong, Titus
• Application Number:
  US14/086,531
• Publication Number:
  US 20150143017A1
• Time in Patent Office: 985 Days
• Field of Search: 710/316
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A system and method are disclosed for an electronic integrated circuit to communicate with different hosts via different interfaces using the same host protocol. The system may use a host interface circuit to select a first set of electrical contacts or a second set of electrical contacts in order for a first host or a second host, respectively, to communicate with the electronic integrated circuit using a host protocol. The method may include switching from communicating with the first host using the first set of electrical contacts to communicating with the second host using the second set of electrical contacts in order for the second host to test the electronic integrated circuit.

Claims

1. An electronic integrated circuit configured to communicate with a first host and a second host, the electronic integrated circuit comprising:

electronic circuitry configured to perform at least one function and configured to communicate with the first host and the second host using a host protocol, wherein the electronic integrated circuit is configured for hardware installation inside the first host and wherein the second host is external to the first host;

a package configured to house the electronic circuitry;

a first set of electrical contacts on an exterior of the package and configured for communication with the first host via the host protocol;

a second set of electrical contacts on the exterior of the package and configured for communication with the second host via the host protocol, wherein the second host uses one or more electrical contacts on an external interface of the first host and the second set of electrical contacts on the exterior of the package in order to communicate with the electronic circuitry; and

a host interface switch configured to input one or more signals to select some or all of the first set of electrical contacts or to select some or all of the second set of electrical contacts in order for one of the first host or the second host to communicate with the electronic circuitry via the host protocol,

wherein the one or more signals are indicative of a mode of the electronic integrated circuit, the mode being selected from at least a test mode and a non-test mode,

wherein, in response to the one or more signals being indicative of the non-test mode, the host interface switch is configured to select the some or all of the first set of electrical contacts in order for the first host to communicate with at least a part of the electronic circuitry in the non-test mode, and

wherein, in response to the one or more signals being indicative of the test mode, the host interface switch is configured to select the some or all of the second set of electrical contacts in order for the second host to test at least a part of the electronic circuitry.

2. The electronic integrated circuit of claim 1, wherein the electronic circuitry comprises a hardware core;

wherein the host interface switch comprises one or more switches configured as an interface between the hardware core and the some or all of the first set of electrical contacts and the some or all of the second set of electrical contacts;

wherein the host interface switch comprises a first configuration in which the some or all of the first set of electrical contacts are in communication with the hardware core;

wherein the host interface switch comprises a second configuration in which the some or all of the second set of electrical contacts are in communication with the hardware core;

wherein, in the first configuration, the hardware core is configured to communicate, via the first set of electrical contacts and the host interface switch, with the first host; and

wherein, in the second configuration, the hardware core configured to communicate, via the second set of electrical contacts and the host interface switch, with the second host.

3. The electronic integrated circuit of claim 1, further comprising:

a mode signal contact on the exterior of the package and configured to input a mode signal; and

logic for generating the one or more signals, the logic configured to;

receive the mode signal;

determine the mode of the electronic integrated circuit based on the received mode signal; and

generate the one or more signals in order to select one of the first set of electrical contacts or the second set of electrical contacts based on the determined mode.

4. The electronic integrated circuit of claim 1, wherein the exterior of package comprises a signal contact configured to input the one or more signals to the electronic integrated circuit.

5. The electronic integrated circuit of claim 1, wherein the electronic circuitry comprises a memory controller and a memory.

6. The electronic integrated circuit of claim 5, further comprising:

a mode signal contact on the exterior of the package and configured to input a mode signal; and

logic for generating the one or more signals, the logic configured to;

receive the mode signal;

determine a mode of the memory controller based on the received mode signal, the mode of the memory controller selected from at least the test mode and the non-test mode; and

in response to determining that the mode of the memory controller is the test mode, generate the one or more signals in order to select the second set of electrical contacts, the second set of electrical contacts configured for the second host to test one or both of the memory controller or the memory.

7. A memory device configured to communicate with a first host and a second host, the memory device comprising:

electronic circuitry configured to communicate using a host protocol and comprising a memory controller and a memory;

a package configured to house the electronic circuitry;

a first set of electrical contacts on an exterior of the package and configured for communication with the first host via the host protocol;

a second set of electrical contacts on the exterior of the package and configured for communication with the second host via the host protocol;

a host interface switch configured to input one or more signals to select some or all of the first set of electrical contacts or to select some or all of the second set of electrical contacts in order for one of the first host or the second host to communicate with the electronic circuitry via the host protocol;

a mode signal contact on the exterior of the package and configured to input a mode signal; and

logic for generating the one or more signals, the logic configured to;

receive the mode signal;

determine a mode of the memory controller based on the received mode signal, the mode of the memory controller selected from at least a test mode and a non-test mode; and

in response to determining that the mode of the memory controller is the test mode, generate the one or more signals in order to select the second set of electrical contacts, the second set of electrical contacts configured for the second host to test one or both of the memory controller or the memory,

wherein the memory device is configured for hardware installation inside the first host; and

wherein the memory device is configured to communicate with the second host, the second host being external to the first host.

8. The memory device of claim 7, wherein the memory device is configured for soldering within the first host;

wherein the second set of electrical contacts are for communication with the second host; and

wherein, when the second set of electrical contacts are selected, the memory device is configured for communication with the second host through the first host in order for the second host to test the memory device without removal of the memory device from within the first host.

9. The memory device of claim 8, wherein the host interface switch comprises a first configuration in which the first set of electrical contacts are in communication with the memory controller;

wherein the host interface switch comprises a second configuration in which the second set of electrical contacts are in communication with the memory controller;

wherein, in the first configuration, a first host controller in the first host is configured to communicate, via the first set of electrical contacts and the host interface switch, with the memory controller; and

wherein, in the second configuration, a second host controller in the second host is configured to communicate, via electrical lines in the first host, the second set of electrical contacts and the host interface switch, with the memory controller.

10. The memory device of claim 9, wherein the first set of electrical contacts comprises at least one power contact configured to receive power from the first host;

and

wherein the at least one power contact is not controlled by the host interface switch so that the memory controller and the memory are electrically connected to the at least one power contact regardless of configuration of the host interface switch.

11. A method for an electronic integrated circuit to communicate with a first host and a second host, the method comprising:

receiving, in at least a portion of the electronic integrated circuit, one or more signals indicative of a non-test mode;

based on the one or more signals indicative of a non-test mode, selecting some or all of a first set of electrical contacts in order for the first host to communicate with at least a part of electronic circuitry of the electronic integrated circuit in the non-test mode;

communicating, via the first set of electrical contacts using a host protocol, with the first host, the electronic integrated circuit being hardware embedded within the first host, the first set of electrical contacts on an exterior of a package of the electronic integrated circuit;

receiving one or more signals indicative of a test mode, to select a second set of electrical contacts for testing of at least a part of the electronic integrated circuit, the second set of electrical contacts on the exterior of the package of the electronic integrated circuit; and

based on the one or more signals indicative of the test mode received, switching, using a host interface switch, from communicating with some or all of the first set of electrical contacts to communicating with some or all of the second set of electrical contacts using the host protocol in order for the second host to test the at least a part of the electronic integrated circuit, the second host being external to the first host,

wherein, while the electronic integrated circuit is hardware embedded within the first host, communicating with the second host to test the at least a part of the electronic integrated circuit comprises using some or all of the second set of electrical contacts and using one or more electrical contacts on an external interface of the first host.

12. The method of claim 11, wherein the electronic circuitry comprises a hardware core;

wherein the host interface switch comprises one or more switches configured as an interface between the hardware core and the some or all of the first set of electrical contacts and the some or all of the second set of electrical contacts;

wherein the host interface switch comprises a first configuration in which the some or all of the first set of electrical contacts are in communication with the hardware core;

wherein the host interface switch comprises a second configuration in which the some or all of the second set of electrical contacts are in communication with the hardware core;

wherein switching, using a host interface switch, from communicating with the some or all of the first set of electrical contacts and communicating with the some or all of the second set of electrical contacts comprises;

switching from the first configuration, in which the hardware core is configured to communicate, via the first set of electrical contacts and the host interface switch, with the first host, to the second configuration, in which the hardware core is configured to communicate, via the second set of electrical contacts and the host interface switch, with the second host.

13. The method of claim 11, further comprising:

receiving a mode signal via a mode signal contact on the exterior of the package;

determining a mode of the electronic integrated circuit based on the received mode signal, the mode being selected from at least the test mode and the non-test mode; and

generating the one or more signals in order to select one of the first set of electrical contacts or the second set of electrical contacts based on the determined mode.

14. The method of claim 11, wherein receiving the one or more signals comprises receiving the one or more signals from a signal contact on the exterior of the package of the electronic integrated circuit.

15. The method of claim 11, wherein the electronic circuitry comprises a memory controller and a memory.

16. The method of claim 15, further comprising:

receiving a mode signal via a mode signal contact on the exterior of the package;

determining a mode of the memory controller based on the received mode signal, the mode of the memory controller selected from at least the test mode and the non-test mode; and

in response to determining that the mode of the memory controller is the test mode, generating the one or more signals in order to select the second set of electrical contacts, the second set of electrical contacts configured for the second host to test one or both of the memory controller or the memory.

17. The method of claim 16, wherein the electronic integrated circuit is configured for soldering within the first host;

wherein the second set of electrical contacts are for communication with the second host; and

wherein switching comprises configuring the electronic integrated circuit for communication with the second host through the first host in order for the second host to test the electronic integrated circuit without removal of the electronic integrated circuit from within the first host.

18. The method of claim 17, wherein the host interface switch comprises a first configuration in which the first set of electrical contacts are in communication with the memory controller;

wherein the host interface switch comprises a second configuration in which the second set of electrical contacts are in communication with the memory controller;

wherein communicating with the first host comprises the memory controller communicating, in the first configuration, with a first host controller in the first host; and

further comprising the memory controller, in the second configuration, communicating with a second host controller in the second host.

19. The method of claim 18, wherein the first set of electrical contacts comprises at least one power contact configured to receive power from the first host;

and

further comprising electrically connecting the memory to the at least one power contact regardless of configuration of the host interface switch.