Smart bridge for memory core

• US 9,406,346 B2
• Filed: 09/28/2011
• Issued: 08/02/2016
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: D'Abreu, Manuel Antonio, Skala, Stephen, Pantelakis, Dimitris, Nair, Radhakrishnan, Pancholi, Deepak
• Primary Examiner(s): Cygiel, Gary W
• Application Number:
  US13/247,532
• Publication Number:
  US 20130007349A1
• Time in Patent Office: 1,770 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.

Claims

1. An apparatus comprising:

a first semiconductor die including a NAND flash memory core, wherein the NAND flash memory core includes a three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels monolithically formed above a substrate of the first semiconductor die and that includes circuitry associated with operation of the multiple memory cells;

a second semiconductor die including;

periphery circuitry associated with the NAND flash memory core;

a first memory interface coupled to the 3D memory core; and

a memory controller interface; and

a third semiconductor die including;

a memory controller, the memory controller configured to communicate with a host device via a host interface; and

a second memory interface coupled to the memory controller interface, wherein the second memory interface is configured to enable communication with the 3D memory core via the second semiconductor die,

wherein the periphery circuitry includes a row decoder configured to operate as a row decoder of the NAND flash memory core, and

wherein the memory controller at the third semiconductor die is further configured to operate as a memory controller of the NAND flash memory core.

2. The apparatus of claim 1, wherein the first semiconductor die does not include a row decoder, and wherein the first semiconductor die and the second semiconductor die do not include a memory controller.

3. The apparatus of claim 1, wherein the second semiconductor die comprises a NAND smart bridge that comprises a NAND management device.

4. The apparatus of claim 1, wherein the row decoder is further configured to decode at least a portion of an address and to select a row of the NAND flash memory core.

5. The apparatus of claim 1, wherein the second semiconductor die further includes multi-ported static random access memory.

6. The apparatus of claim 5, wherein the second semiconductor die further includes circuitry configured to concurrently process multiple word lines of data at the multi-ported static random access memory.

7. The apparatus of claim 6, wherein the circuitry is further configured to:

receive the multiple word lines of data from the 3D memory core; and

process the multiple word lines of data to detect at least one of an interference condition of the 3D memory core, a program disturb condition of the 3D memory core, or a read disturb condition of the 3D memory core.

8. The apparatus of claim 6, wherein the multiple word lines of data are configured to be sensed from a single word line of the NAND flash memory core using different sets of read voltages, and wherein the multi-ported static random access memory is configured to receive the multiple word lines of data from the first semiconductor die.

9. The apparatus of claim 6, wherein the second semiconductor die further includes a first error correction coding (ECC) engine that is configured to perform error correction processing of the multiple word lines of data.

10. The apparatus of claim 9, wherein the first ECC engine is further configured to encode first data to be stored in the 3D memory core, and wherein the second semiconductor die further includes a second ECC engine configured to encode second data concurrently with the first ECC engine encoding the first data.

11. The apparatus of claim 6, wherein the circuitry is further configured to process the multiple word lines of data to detect specific data patterns.

12. The apparatus of claim 6, wherein the circuitry is further configured to process the multiple word lines of data by scrambling data to be stored to the 3D memory core.

13. The apparatus of claim 1, further comprising a fourth semiconductor die including a NAND flash memory, wherein the second semiconductor die further includes a second memory device interface coupled to the NAND flash memory.

14. The apparatus of claim 1, wherein the multiple memory cells and the multiple physical levels are integrated within a single die that includes the substrate, the multiple memory cells including a first memory cell located at a first distance from the substrate and a second memory cell located at a second distance from the substrate, the second distance greater than the first distance.

15. The apparatus of claim 1, wherein the periphery circuitry further includes an error correction coding (ECC) engine.

16. The apparatus of claim 15, wherein the periphery circuitry is configured to process multiple word lines of data to scramble data to be stored to the NAND flash memory core.

17. The apparatus of claim 1, wherein the periphery circuitry further includes multi-ported static random access memory (SRAM).

18. The apparatus of claim 17, wherein the periphery circuitry is configured to concurrently process multiple word lines of data at the multi-ported SRAM.

19. The apparatus of claim 18, wherein the periphery circuitry is further configured to:

receive the multiple word lines of data from the NAND flash memory core; and

process the multiple word lines of data to detect at least one of an interference condition,

a program disturb condition, or a read disturb condition.

20. The apparatus of claim 18, wherein the multiple word lines of data correspond to a single word line read with different sets of read voltages, and wherein the periphery circuitry is further configured to perform error correction processing of the multiple word lines of data.

21. The apparatus of claim 18, wherein the periphery circuitry is further configured to process the multiple word lines of data to detect specific data patterns.

22. The apparatus of claim 17, wherein the periphery circuitry is further configured to operate the multi-ported SRAM as a cache memory.

23. The apparatus of claim 22, wherein the periphery circuitry further includes control logic, and wherein the control logic comprises at least one of a finite state machine and a micro-programmed engine.

24. The apparatus of claim 1, further comprising a fourth die including a second NAND flash memory core, wherein the periphery circuitry is configured to generate control signals to control operation of the NAND flash memory core and to control operation of the second NAND flash memory core, and wherein the periphery circuitry comprises:

a first error correction coding (ECC) engine configured to encode first data to be stored in the NAND flash memory core; and

a second ECC engine configured to encode second data to be stored in the second NAND flash memory core.

25. The apparatus of claim 1, wherein the periphery circuitry is configured to perform a first error correction coding (ECC) operation, wherein the memory controller is further configured to perform a second ECC operation, and wherein the first ECC operation uses a different error correction code than the second ECC operation.

26. A method of NAND smart bridge operation, the method comprising:

receiving data for storage at a NAND flash memory core at a first semiconductor die, wherein the NAND flash memory core includes a three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate and that includes circuitry associated with operation of the multiple memory cells, wherein the data is received at a second semiconductor die that includes periphery circuitry for the NAND flash memory core, and wherein the data is received from a memory controller that is on a third semiconductor die, the third semiconductor die coupled to the second semiconductor die; and

sending a control signal from the second semiconductor die to the NAND flash memory core of the first semiconductor die, wherein the periphery circuitry generates the control signal to affect operation of the NAND flash memory in response to receiving one or more commands from the memory controller on the third semiconductor die.

27. The method of claim 26, wherein the first semiconductor die lacks circuitry to generate the control signal and wherein the first semiconductor die and the second semiconductor die do not include a memory controller.

28. The method of claim 26, wherein the periphery circuitry includes at least one of a processor, an error correction coding (ECC) engine, a row decoder, a charge pump, and a multi-ported static random access memory (SRAM).

29. The method of claim 26, further comprising sending a codeword from the second semiconductor die to the NAND flash memory core, the codeword corresponding to the received data, wherein the NAND flash memory core is responsive to the control signal to store the codeword.

30. A method of NAND smart bridge operation, the method comprising:

sending a control signal to a NAND flash memory core at a first semiconductor die, the control signal sent from a second semiconductor die, wherein the NAND flash memory core comprises a three-dimensional (3D) memory core that includes multiple memory cells arranged in multiple physical levels above a substrate and that includes circuitry associated with operation of the multiple memory cells; and

receiving, at the second semiconductor die, a representation of a codeword from the NAND flash memory core, wherein the representation of the codeword is received at periphery circuitry for the NAND flash memory core, wherein the periphery circuitry is within the second semiconductor die, and wherein the periphery circuitry generates the control signal to affect operation of the NAND flash memory core in response to receiving one or more commands from a memory controller on a third semiconductor die coupled to the second semiconductor die.

31. The method of claim 30, wherein the periphery circuitry includes at least one of a processor, an error correction coding (ECC) engine, a row decoder, a charge pump, and a multi-ported static random access memory (SRAM).

32. The method of claim 30, wherein the first semiconductor die lacks circuitry to generate the control signal, and wherein the first semiconductor die and the second semiconductor die do not include a memory controller.