Memory elements and cross point switches and arrays for same using nonvolatile nanotube blocks

• US 9,406,349 B2
• Filed: 05/02/2014
• Issued: 08/02/2016
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Huang, X. M. Henry, Rueckes, Thomas, Sivarajan, Ramesh
• Primary Examiner(s): Gebremariam, Samuel
• Application Number:
  US14/268,305
• Publication Number:
  US 20140241023A1
• Time in Patent Office: 823 Days
• Field of Search: 257/254, 257/415, 257/420
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10K 10/50 : Bistable switching devices
• CPC Class Codes: H10K 85/221 : Carbon nanotubes
• CPC Class Codes: Y10S 977/943 : Information storage or retrieval using nanostructure

Abstract

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Claims

1. An array of nonvolatile nanotube block switches, comprising:

a first plurality of conductive traces arranged substantially parallel to each other in a first plane;

a second plurality of conductive traces arranged substantially parallel to each other in a second plane, said second plane substantially parallel to said first plane;

a plurality of nonvolatile nanotube blocks arranged in a third plane, said third plane substantially parallel to and situated between said first plane and said second plane;

wherein said nonvolatile nanotube blocks comprise a patterned nanotube fabric having a top surface and a bottom surface;

wherein each nonvolatile nanotube block within said plurality of nonvolatile nanotube blocks is situated at a cross point of a conductive trace within said first plurality of conductive traces and a conductive trace within said second plurality of conductive traces; and

wherein said top surface of each nonvolatile nanotube block within said plurality of nonvolatile nanotube blocks is in electrical communication with a conductive trace within said first plurality of conductive traces and said bottom surface of each nonvolatile nanotube block within said plurality of nonvolatile nanotube blocks is in electrical communication with a conductive trace within said second plurality of conductive traces.

2. The array of claim 1 wherein said conductive traces within said first plurality of conductive traces are substantially perpendicular to said conductive traces within said second plurality of conductive traces.

3. The array of claim 1 wherein each of said plurality of nonvolatile nanotube blocks is uniquely addressable and programmable via one conductive trace within said first plurality of conductive traces and one conductive trace within said second plurality of conductive traces.

4. The array of claim 1 wherein at least one of the height, width, or depth of said nonvolatile nanotube blocks corresponds to the minimum feature size of a fabrication process used to realize said array.

5. The array of claim 1 further comprising a memory operation circuit including a circuit for generating and applying electrical stimuli to said first plurality of said conductive traces and said second plurality of conductive traces.

6. The array of claim 5 wherein said electrical stimuli is capable of inducing a change in the resistance of a preselected nonvolatile nanotube block.

7. The array of claim 6 wherein said change in resistance comprises a change between a first resistance state and a second resistance state, the first resistance state being a substantially higher resistance than the second resistance state.

8. The nanotube memory array of claim 7 wherein the first resistance state comprises a first information state and the second resistance state comprises a second information state.

9. The array of claim 5 wherein said electrical stimuli is capable of determining the resistive state of a preselected nonvolatile nanotube block without altering the resistive state of said preselected nonvolatile nanotube block.

10. The array of claim 1 wherein for said at least two nonvolatile nanotube blocks a change of resistance in a first nonvolatile nanotube block is substantially unaffected by a change of resistance in a second nonvolatile nanotube block.

11. The array of claim 1 wherein said patterned nanotube fabric comprises a plurality of unaligned nanotubes providing a plurality of conductive pathways through said patterned nanotube fabric.

12. The array of claim 1 where said nonvolatile nanotube blocks are memory cells capable of storing at least one bit of data.

13. The array of claim 12 wherein said array is a memory array.