Sense amplifier

• US 9,406,355 B1
• Filed: 06/16/2015
• Issued: 08/02/2016
• Est. Priority Date: 06/16/2015
• Status: Active Grant

• Current Assignee: National Tsing Hua University
• Original Assignee: National Tsing Hua University
• Inventors: Chang, Meng-Fan, Chen, Yu-Lin
• Primary Examiner(s): Tran, Michael
• Application Number:
  US14/740,288
• Time in Patent Office: 413 Days
• Field of Search: 365/189.011, 365/203
• US Class Current: 1/1
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

The present disclosure provides a sense amplifier. The sense amplifier includes a first inverting circuit, a second inverting circuit, a capacitor, and a write-back path circuit. The first inverting circuit has a first input end and a first output end, and the first input end receives a first bit line signal from a memory cell. The second inverting circuit has a second input end and a second output end, wherein the second input is coupled to the first output end, and the second output end is coupled to the first input end, and the second input end receives a second bit line signal from the memory cell. The capacitor receives a boost signal and generates a boosted voltage according to the boost signal during a write-back timing period. The write-back path circuit transports the boosted voltage to one of the first and second input ends during the write-back timing period.

Claims

1. A sense amplifier, comprising:

a first inverting circuit, having a first input end and a first output end, and the first input end receiving a first bit line signal from a memory cell;

a second inverting circuit, having a second input end and a second output end, wherein the second input is coupled to the first output end, and the second output end is coupled to the first input end, and the second input end receives a second bit line signal from the memory cell;

a capacitor, receiving a boost signal and generating a boosted voltage according to the boost signal during a write-back timing period;

a write-back path circuit, coupled to the capacitor and transporting the boosted voltage to one of the first and second input ends during the write-back timing period according to the first and second bit line signals,

wherein the write-back path circuit comprises;

a first switch, coupled between the capacitor and the second input end, and being controlled by the first bit line signal to be turned on or cut off; and

a second switch, coupled between the capacitor and the first input end, and being controlled by the second bit line signal to be turned on or cut off.

2. The sense amplifier according to claim 1, wherein the first bit line signal and the second bit line signal are complementary during the write-back timing period, and on-off status of the first and second switches are complementary during the write-back timing period.

3. The sense amplifier according to claim 1, wherein the first switch comprises:

a first transistor, having a first end, second end, and control end, wherein the first end of the first transistor receives the boosted voltage, the second end of the first transistor is coupled to the second input end, and the control end of the first transistor receives the first bit line signal; and

the second switch comprises;

a second transistor, having a first end, second end, and control end, wherein the first end of the second transistor receives the boosted voltage, the second end of the second transistor is coupled to the first input end, and the control end of the first transistor receives the second bit line signal.

4. The sense amplifier according to claim 3, further comprising:

a first power path switch, coupled between ground ends of the first and second inverting circuit and a reference ground, and being controlled by a sense enable signal for being turned on or cut off; and

a second power path switch, coupled between power receiving ends of the first and second inverting circuit and an operation power, and being controlled by an inverted sense enable signal for being turned on or cut off.

5. The sense amplifier according to claim 4, wherein during a charge sharing timing period of a reading timing period, the first and second power path switches and the first and second switches are cut off, during a data sensing timing period of the reading timing period, the first and second power path switches are turned on and merely one of the first and second switches is turned on, during the write-back timing period of the reading timing period, the first and second power path switches are cut off, and the boosted voltage is provided to one of the first and second bit line signal to be written back to the memory cell.

6. The sense amplifier according to claim 5, wherein the charge sharing timing period is before the data sensing timing period, and the data sensing timing period is before the write-back timing period.

7. The sense amplifier according to claim 1, wherein a voltage level of the boost signal is boosted from a first voltage to a second voltage level during the wire-back timing period, wherein the second voltage level is larger than the first voltage level.

8. The sense amplifier according to claim 1, wherein the first inverting circuit comprises:

a first transistor, having a first end, second end, and a control end, wherein the first end of the first transistor receives an operation power, the second end of the first transistor is coupled to the first output end, and the control end of the first transistor is coupled to the first input end; and

a second transistor, having a first end, second end, and a control end, wherein the first end of the second transistor is coupled to the second end of the first transistor, the second end of the second transistor is coupled to a reference ground, and the control end of the second transistor is coupled to the first input end; and

the second inverting circuit comprises;

a third transistor, having a first end, second end, and a control end, wherein the first end of the third transistor receives the operation power, the second end of the third transistor is coupled to the second output end, and the control end of the third transistor is coupled to the second input end; and

a fourth transistor, having a first end, second end, and a control end, wherein the first end of the fourth transistor is coupled to the second end of the third transistor, the second end of the fourth transistor is coupled to the reference ground, and the control end of the fourth transistor is coupled to the second input end.

9. The sense amplifier according to claim 1, wherein an operating power of the sense amplifier is set between 0.5˜

0.9 volt.