Driver circuit, display device including the driver circuit, and electronic appliance including the display device

• US 9,406,398 B2
• Filed: 10/31/2013
• Issued: 08/02/2016
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Miyake, Hiroyuki
• Primary Examiner(s): O NEILL, PATRICK
• Application Number:
  US14/068,012
• Publication Number:
  US 20140056400A1
• Time in Patent Office: 1,006 Days
• Field of Search: 377/2, 377/64, 377 77- 81, 327/108, 326/82, 326/83, 326 95- 98
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit.

Claims

1. A semiconductor device comprising a shift register circuit, the shift register circuit comprising:

a first transistor;

a second transistor; and

a third transistor,

wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a gate electrode, a gate insulating film, and an oxide semiconductor layer,

wherein the first transistor, the second transistor, and the third transistor are depletion-mode transistors,

wherein one of a source and a drain of the first transistor is connected to one of a source and a drain of the second transistor,

wherein a gate of the first transistor is connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the third transistor is connected to a gate of the second transistor,

wherein a first signal is input to a gate of the third transistor, and

wherein an amplitude voltage of the first signal is greater than a potential difference between the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a display device.

3. An electronic device comprising a display portion, an operation key, an image receiving portion, a housing, and a keyboard, wherein the display portion includes the display device according to claim 2.

4. The semiconductor device according to claim 1, wherein the gate of the first transistor is in direct contact with the other of the source and the drain of the first transistor.

5. The semiconductor device according to claim 1, wherein the gate insulating film comprises silicon.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a crystallinity of 80 % or higher.

7. A semiconductor device comprising a shift register, the shift register comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

a fifth transistor,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor includes a gate electrode, a gate insulating film, and an oxide semiconductor layer,

wherein the first transistor, the second transistor, and the third transistor are depletion-mode transistors,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor have a same conductivity type,

wherein one of a source and a drain of the first transistor and one of a source and a drain of the second transistor are in a same conductive layer,

wherein the one of the source and the drain of the first transistor is connected to the one of the source and the drain of the second transistor,

wherein a gate of the first transistor is connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the third transistor is connected to a gate of the second transistor,

wherein one of a source and a drain of the fourth transistor is connected to the one of the source and the drain of the second transistor,

wherein one of a source and a drain of the fifth transistor is connected to the gate of the second transistor,

wherein a first signal is input to a gate of the third transistor,

wherein a second signal is input to a gate of the fourth transistor,

wherein the second signal is input to a gate of the fifth transistor,

wherein an amplitude voltage of the first signal is greater than a potential difference between the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor,

wherein an amplitude voltage of the second signal is greater than the potential difference between the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor, and

wherein the other of the source and the drain of the second transistor is connected to a wiring through which a potential lower than a reference potential is supplied.

8. The semiconductor device according to claim 7, wherein the semiconductor device is a display device.

9. An electronic device comprising a display portion, an operation key, an image receiving portion, a housing, and a keyboard, wherein the display portion includes the display device according to claim 8.

10. The semiconductor device according to claim 7, wherein the gate of the first transistor is in direct contact with the other of the source and the drain of the first transistor.

11. The semiconductor device according to claim 7, wherein the gate insulating film comprises silicon.

12. The semiconductor device according to claim 7, wherein the oxide semiconductor layer has a crystallinity of 80 % or higher.

13. A semiconductor device comprising a shift register, the shift register comprising:

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a gate electrode, a gate insulating film, and an oxide semiconductor layer,

wherein the first transistor, the second transistor, and the third transistor are depletion-mode transistors,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have a same conductivity type,

wherein one of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor,

wherein a gate of the first transistor is connected to the other of the source and the drain of the first transistor,

wherein one of a source and a drain of the third transistor is connected to a gate of the second transistor,

wherein one of a source and a drain of the fourth transistor is connected to the one of the source and the drain of the second transistor,

wherein a first signal is input to a gate of the third transistor,

wherein a second signal is input to a gate of the fourth transistor,

wherein an amplitude voltage of the first signal is greater than a potential difference between the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor, and

wherein an amplitude voltage of the second signal is greater than the potential difference between the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor.