High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor

• US 9,406,516 B2
• Filed: 04/07/2015
• Issued: 08/02/2016
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Ke, Jian-Cun, Yang, Chih-Wei, Lo, Kun-Yuan, Hsu, Chia-Fu, Wang, Shao-Wei
• Primary Examiner(s): Dang, Truong Q
• Assistant Examiner(s): REDDINGTON, PATRICIA D
• Application Number:
  US14/680,078
• Publication Number:
  US 20150214060A1
• Time in Patent Office: 483 Days
• Field of Search: 257/411, 438/142
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming an interfacial layer on the substrate;

forming a high-k dielectric layer on the interfacial layer;

forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;

performing a thermal treatment;

removing the first BBM layer completely;

forming a second BBM layer on and contact the high-k dielectric layer after removing the first BBM layer completely, wherein the first BBM layer and the second BBM layer comprise same material;

forming a sacrificial layer on the second BBM layer; and

patterning the sacrificial layer to form a dummy gate.

2. The method of claim 1, further comprising performing a pre-clean before forming the interfacial layer.

3. The method of claim 1, further comprising:

forming a spacer on the sidewall of the dummy gate;

forming a source/drain region in the substrate adjacent to the spacer;

forming a contact etch stop layer on the dummy gates;

forming an interlayer dielectric layer (ILD) on the contact etch stop layer; and

performing a replacement metal gate (RMG) process to form the dummy gate into metal gate.

4. The method of claim 1, wherein the sacrificial layer comprises amorphous silicon or polysilicon.

5. The method of claim 1, wherein the interfacial layer comprises silicon oxide.

6. The method of claim 1, wherein the first BBM layer and the second BBM layer comprise TiN.

7. The method of claim 1, further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment.

8. The method of claim 7, further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer.

9. The method of claim 7, wherein the silicon layer comprises amorphous silicon.

10. The method of claim 7, wherein the thickness of the silicon layer is between 100 Angstroms to 300 Angstroms.

11. The method of claim 1, wherein the temperature of the thermal treatment is between 700-1000°

C.