Compliant bipolar micro device transfer head with silicon electrodes

• US 9,406,541 B2
• Filed: 12/02/2015
• Issued: 08/02/2016
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Golda, Dariusz, Bibl, Andreas
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US14/957,331
• Publication Number:
  US 20160086837A1
• Time in Patent Office: 244 Days
• Field of Search: 257/619, 257/623, 257/774, 257/E29.324, 257/288, 438/130, 438/128, 438/158, 438/250, 438/251, 438/253, 438/254, 438/261, 438/263, 438/276, 438/30, 438/39, 438/396
• US Class Current: 1/1
• CPC Class Codes: B32B 38/18 Handling of layers or the laminate
• CPC Class Codes: B81C 99/002 Apparatus for assembling MEMS, e.g. micromanipulators micromanipulators per se B25J7/00
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H02N 13/00 : Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
• CPC Class Codes: Y10T 156/17 : Surface bonding means and/or assemblymeans with work feeding or handling means

Abstract

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

Claims

1. An electrostatic transfer head array comprising:

a base substrate;

an insulating layer on the base substrate;

a device layer on the insulating layer, the device layer comprising;

a first trace interconnect integrally formed with a first array of electrodes; and

a second trace interconnect integrally formed with a second array of electrodes;

wherein the first array of electrodes is electrically insulated from the second array of electrodes;

an array of dielectric joints between the first array of electrodes and the second array of electrodes;

wherein the first trace interconnect and the second trace interconnect are parallel to one another, and the dielectric joints are perpendicular to the first trace interconnect and the second trace interconnect.

2. The electrostatic transfer head array of claim 1, wherein each electrode of the first array of electrodes and the second array of electrodes is deflectable toward the base substrate.

3. The electrostatic transfer head array of claim 2, further comprising a cavity in the base substrate, and the first array of electrodes and the second array of electrodes are deflectable into the cavity.

4. The electrostatic transfer head array of claim 2, further comprising an array of cavities in the base substrate, and the first array of electrodes and the second array of electrodes are deflectable into the array of cavities.

5. The electrostatic transfer head array of claim 1:

wherein the first array of electrodes comprises a first array of electrode leads and a first array of mesa structures; and

wherein the second array of electrodes comprises a second array of electrode leads and a second array of mesa structures.

6. The electrostatic transfer head array of claim 5, wherein the array of dielectric joints joins the first array of mesa structures to the second array of mesa structures.

7. The electrostatic transfer head array of claim 1, further comprising a first voltage source connection electrically connected with the first trace interconnect and a second voltage source connection electrically connected with the second trace interconnect.

8. The electrostatic transfer head array of claim 7, wherein the first voltage source connection comprises a first via opening extending though the base substrate, and the second voltage source connection comprises a second via opening extending though the base substrate.

9. The electrostatic transfer head array of claim 8, wherein the first voltage source connection comprises a third via opening extending through the device layer, and the second voltage source connection comprises a fourth via opening extending through the device layer.

10. The electrostatic transfer head array of claim 9, further comprising a dielectric layer on the device layer.

11. The electrostatic transfer head array of claim 10, further comprising a first conductive layer within the third via opening, and a second conductive layer within the fourth via opening.

12. The electrostatic transfer head array of claim 11, wherein the first conductive layer is directly on the device layer, and the second conductive layer is directly on the device layer.

13. The electrostatic transfer head array of claim 12, wherein the first conductive layer is directly on a top surface of the device layer, and the second conductive layer is directly on the top surface of device layer.

14. The electrostatic transfer head array of claim 12, wherein the first conductive layer is directly on the dielectric layer, and the second conductive layer is directly on the dielectric layer.

15. The electrostatic transfer head array of claim 1, wherein the base substrate comprises silicon.

16. The electrostatic transfer head array of claim 15, wherein the device layer comprises silicon.