Integrated circuit and design structure having reduced through silicon via-induced stress

• US 9,406,562 B2
• Filed: 01/13/2011
• Issued: 08/02/2016
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bonn, Jeffrey P., Goplen, Brent A., Kinsman, Brian L., Rassel, Robert M., Sprogis, Edmund J., Vanslette, Daniel S.
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US13/005,883
• Publication Number:
  US 20120181700A1
• Time in Patent Office: 2,028 Days
• Field of Search: 257/774, 257/E23.011, 716/100, 716/119
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Claims

1. An integrated circuit comprising:

a substrate; and

a plurality of through silicon via (TSV) cells in the substrate and each arranged in a plurality of rows each having a shared horizontal axis and a plurality of columns each having a shared vertical axis, each of the plurality of TSV cells including a plurality of TSVs each having a substantially same size and a substantially same orientation, the plurality of TSV cells comprising;

a first group of TSV cells, the through silicon vias (TSVs) of which have a first orientation; and

a second group of TSV cells, the TSVs of which have a second orientation substantially perpendicular to the first orientation,

wherein each of the TSV cells adjacent to a first TSV cell of the first group is a TSV cell of the second group, wherein each adjacent TSV cell is separated from the first TSV cell by less than a threshold distance independent from a size of the first TSV cell, and wherein an arrangement of adjacent TSV cells in the integrated circuit reduces TSV-induced stresses in the substrate between the first TSV cell of the first group and each of the adjacent TSV cells of the second group.

2. The integrated circuit of claim 1, wherein the first group of TSV cells comprises between about 40% and about 60% of the TSVs of the integrated circuit.

3. The integrated circuit of claim 1, wherein the second group of TSV cells comprises between about 40% and about 60% of the TSVs of the integrated circuit.

4. The integrated circuit of claim 1, wherein each of the first group of TSV cells and the second group of TSV cells comprises about 50% of the TSVs of the integrated circuit.

5. The integrated circuit of claim 1, wherein each TSV cell adjacent to each TSV cell of the first group includes TSVs having the orientation of the second group.

6. The integrated circuit of claim 1, wherein the first orientation of at least one of the TSVs in the first group is predetermined in a preliminary integrated circuit design.

7. A non-transitory computer-readable medium storing code representative of a design structure realized upon execution of the code by a computer system, the code representative of the design structure including code representing a circuit, the code comprising:

code representing an integrated circuit (IC), the IC including;

a substrate; and

a plurality of through silicon via (TSV) cells in the substrate and each arranged in a plurality of rows each having a shared horizontal axis and a plurality of columns each having a shared vertical axis, the plurality of TSV cells each including a plurality of through silicon vias (TSVs) each having a substantially same size and a substantially same orientation, the plurality of TSV cells comprising;

a first group of TSV cells, the TSVs of which have a first orientation; and

a second group of TSV cells, the TSVs of which have a second orientation substantially perpendicular to the first orientation,

wherein each of the TSV cells adjacent to a first TSV cell of the first group is a TSV cell of the second group, wherein each adjacent TSV cell is separated from the first TSV cell by less than a threshold distance independent from a size of the first TSV cell, and wherein an arrangement of adjacent TSV cells in the integrated circuit reduces TSV-induced stresses in the substrate between the first TSV cell of the first group and each of the adjacent TSV cells of the second group.

8. The non-transitory computer-readable medium of claim 7, wherein the first group of TSV cells comprises between about 40% and about 60% of the TSVs of the integrated circuit.

9. The non-transitory computer-readable medium of claim 7, wherein the second group of TSV cells comprises between about 40% and about 60% of the TSVs of the integrated circuit.

10. The non-transitory computer-readable medium of claim 7, wherein each of the first group of TSV cells and the second group of TSV cells comprises about 50% of the TSVs of the integrated circuit.

11. The non-transitory computer-readable medium of claim 7, wherein the code representing the IC includes a schematic.

12. The non-transitory computer-readable medium of claim 7, wherein the code representing the IC is written in a hardware description language.

13. The non-transitory computer-readable medium of claim 7, wherein the first orientation of at least one of the TSVs in the first group is predetermined in a preliminary integrated circuit design.