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Integrated circuit and design structure having reduced through silicon via-induced stress

  • US 9,406,562 B2
  • Filed: 01/13/2011
  • Issued: 08/02/2016
  • Est. Priority Date: 01/13/2011
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a substrate; and

    a plurality of through silicon via (TSV) cells in the substrate and each arranged in a plurality of rows each having a shared horizontal axis and a plurality of columns each having a shared vertical axis, each of the plurality of TSV cells including a plurality of TSVs each having a substantially same size and a substantially same orientation, the plurality of TSV cells comprising;

    a first group of TSV cells, the through silicon vias (TSVs) of which have a first orientation; and

    a second group of TSV cells, the TSVs of which have a second orientation substantially perpendicular to the first orientation,wherein each of the TSV cells adjacent to a first TSV cell of the first group is a TSV cell of the second group, wherein each adjacent TSV cell is separated from the first TSV cell by less than a threshold distance independent from a size of the first TSV cell, and wherein an arrangement of adjacent TSV cells in the integrated circuit reduces TSV-induced stresses in the substrate between the first TSV cell of the first group and each of the adjacent TSV cells of the second group.

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