Integrated circuit and design structure having reduced through silicon via-induced stress
First Claim
1. An integrated circuit comprising:
- a substrate; and
a plurality of through silicon via (TSV) cells in the substrate and each arranged in a plurality of rows each having a shared horizontal axis and a plurality of columns each having a shared vertical axis, each of the plurality of TSV cells including a plurality of TSVs each having a substantially same size and a substantially same orientation, the plurality of TSV cells comprising;
a first group of TSV cells, the through silicon vias (TSVs) of which have a first orientation; and
a second group of TSV cells, the TSVs of which have a second orientation substantially perpendicular to the first orientation,wherein each of the TSV cells adjacent to a first TSV cell of the first group is a TSV cell of the second group, wherein each adjacent TSV cell is separated from the first TSV cell by less than a threshold distance independent from a size of the first TSV cell, and wherein an arrangement of adjacent TSV cells in the integrated circuit reduces TSV-induced stresses in the substrate between the first TSV cell of the first group and each of the adjacent TSV cells of the second group.
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Accused Products
Abstract
Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.
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Citations
13 Claims
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1. An integrated circuit comprising:
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a substrate; and a plurality of through silicon via (TSV) cells in the substrate and each arranged in a plurality of rows each having a shared horizontal axis and a plurality of columns each having a shared vertical axis, each of the plurality of TSV cells including a plurality of TSVs each having a substantially same size and a substantially same orientation, the plurality of TSV cells comprising; a first group of TSV cells, the through silicon vias (TSVs) of which have a first orientation; and a second group of TSV cells, the TSVs of which have a second orientation substantially perpendicular to the first orientation, wherein each of the TSV cells adjacent to a first TSV cell of the first group is a TSV cell of the second group, wherein each adjacent TSV cell is separated from the first TSV cell by less than a threshold distance independent from a size of the first TSV cell, and wherein an arrangement of adjacent TSV cells in the integrated circuit reduces TSV-induced stresses in the substrate between the first TSV cell of the first group and each of the adjacent TSV cells of the second group. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A non-transitory computer-readable medium storing code representative of a design structure realized upon execution of the code by a computer system, the code representative of the design structure including code representing a circuit, the code comprising:
code representing an integrated circuit (IC), the IC including; a substrate; and a plurality of through silicon via (TSV) cells in the substrate and each arranged in a plurality of rows each having a shared horizontal axis and a plurality of columns each having a shared vertical axis, the plurality of TSV cells each including a plurality of through silicon vias (TSVs) each having a substantially same size and a substantially same orientation, the plurality of TSV cells comprising; a first group of TSV cells, the TSVs of which have a first orientation; and a second group of TSV cells, the TSVs of which have a second orientation substantially perpendicular to the first orientation, wherein each of the TSV cells adjacent to a first TSV cell of the first group is a TSV cell of the second group, wherein each adjacent TSV cell is separated from the first TSV cell by less than a threshold distance independent from a size of the first TSV cell, and wherein an arrangement of adjacent TSV cells in the integrated circuit reduces TSV-induced stresses in the substrate between the first TSV cell of the first group and each of the adjacent TSV cells of the second group. - View Dependent Claims (8, 9, 10, 11, 12, 13)
Specification